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0< $ dB , H P X 8 ( : @ߧ $ T% - @-$
0< $ dBP , H P X 8 ( : @ߧ $ T%$ @-$
0< X - dB , H P 8 ( : @ߧ - T%$
@-$ $ X< dBp < 7 # ,7 Y 0 x H7 P 8 ( : @ߧ $ T%$
@-< 0 - dBӸ , H P X 8 ( : @ߧ - T%$
@-$ $ < dB , 0 H P X 8 ( : @ߧ $ T% - @-<4B #$
4B Y x 4B < ,dBp 0 H P X$ 8 ( : @< -7 # T%ߧ @-7 Y$
x 0< 7 $ dB $ , H P X 8 ( : @< -7 # T%ߧ @-7 Y$
x 0< 7 $ dBX $ , H P X 8 ( : @< -7 # T%ߧ @-7 Y$
x 0< 7 $ dB $ , H P X 8 ( : @< -7 # T%ߧ @-7 Y$
x 0< 7 $ dBp $ , H P X 8 ( : @< -7 # T%ߧ @-7 Y$
x 0< 7 $ dB $ , H P X 8 ( : @< -7 # T%ߧ @-7 Y$
x 0< 7 $ dBא < ,7 # H P7 Y X x 87 ( : @ߧ $ T% - @-<4B #$
0 4B Y x 4B < ,dBد 0 H P X 8 ( : @< -7 # T%ߧ @-7 Y$
0 x 0< 7 $ $ dB( < ,7 # H P7 Y X x 87 ( : @ߧ $ T% - @-<4B #$
0 4B Y$ x 4B < dBؐ , 0 H P X$
0 8 ( : @< <7 #4 # T%ߧ 7 Y , @- x$ 4 Y 7 .x< - 4 $ ,dB 0< H7 # P X7 Y 8 x (7 : @ߧ $ T% - @-<4B #$
0 4B Y x4B $ $ X< dBx , 0 H P 8 ( : @<< 4 #7 # , T%ߧ 4 Y @- .x$
0 07 Y4 x < -7 $ dB < ,7 # H P7 Y X x 87 ( : @ߧ $ T% - @-<4B #$
0 4B Y$ x 4B < dBڐ , 0 H P X$
0 8 ( : @< <7 #4 # T%ߧ 7 Y , @- x$ 4 Y 7 .x< - 4 $ ,dB 0< H7 # P X7 Y 8 x (7 : @ߧ $ T% - @-<4B #$
0 4B Y x4B $
$ X< dB۰ , 0 H P 8 ( : @ߧ <4 # T%ߩ , <4 #4 Y < @-4 Y .x >x<$ - X4X 4` dB , 0 H P 8 ( : @<$ V%4 # @-<4B # < 4 Y4B Y >xߩ x4BX4` < 0 -$ dB@ , H P X 8 ( : @< - V%7 # @-<4B # 7 Y4B Y xߩ x4B`7X < $
dB܈ , 0 H P X$ 8 ( : @<< 4 #7 #ߩ V% < @-4 Y$
7 Y 0 >x x< -4X 7` $ dB $ , H P X 8 ( : @<< 4 #7 #ߩ V% < @-4 Y$
7 Y 0 >x x< -4X 7` $ dBX $ , H P X 8 ( : @<< 4 #7 #ߩ V% < @-4 Y$
7 Y 0 >x x< -4X 7` $ dBݰ < ,7 # H P7 Y X x 87` ( : @<$ @4 # V%ߩ < @-4 Y$ >x X< 8$
0 - 4X dB < 6R # ,6R H 8 PfP ($ : @ߩ $ V%$ @ @-< - dBP 0fT XfU , H P 8 ( : @ߩ $ @ V% - 0 @- $ X< dBި $ , H P 8 ( : @ߩ $ V%$ @ @-< - dB௧ 0 , H P X 8 ( : @ߩ < V% - @- $ @ 0< dBp , H P X 8 ( : @ߩ < V%$ @ @-< - dBد 0 , H P X< @ 8 ( : @ߩ $ @ V% - 0 @- $ X< dB@ $ , H P 8 ( : @ߩ < V%$ @ @-< - dB 0 , H P X 8 ( : @ߩ < V% - @- $ @ 0< dB , H P X 8 ( : @ߩ < V%$ @ @-< - dB 0 , H P X< 8 ( : @ߩ $ @ V% - 0 @- $ X< dBH $ , H P 8 ( : @ߩ < V%$ @ @-< 0 - dB , H P X 8 ( : @ߩ < V% - @- $ @ 0< dBp < 6R # , H6R P 8 X6R 8fP ( : @ߩ - V%$ @ @- < dB , 0 H P X 8 ( : @ߩ $ @ V%$ < @-< 0 - dB0 , H P X$ @ 8 ( : @ߩ $ V%< @-< X - dB` fT fU , 0 H P 8 ( : @ߩ $ V% - X @- $ < dB , 0 H P 8 ( : @ߩ $ V% - 0 @-<$ dB , H P X 8 ( : @ߩ $ V% - @- $ @ 0< dB , H P X 8 ( : @ߩ $ @ V%$ @-< 0 - dB , H P X$ @ 8 ( : @ߩ $ V%$ @-< X - dBp , 0 H P 8 ( : @ߩ - V%$ @- $ < ,dB H 0 P< X6s 8 (< : @6s Cf1 V% x @-< 0$ $ - $ ,dB鈯 H P X 8 ( : @$ - V%$ @ @- $ < dB , 0 H P X$ @ 8 ( : @$ $ V%$ @-< X - dB , 0 H P 8 ( : @ߦ $ V%$ @-< X - dB , 0$ H P 8 ( : @ߦ $ @ V% - 0 @- < dB8 , H P X 8 ( : @ߦ $ V% - @- $ @ 0< dB , H P X 8 ( : @ߦ $ V% - @- < $ @ dB , 0 H P X 8 ( : @ߦ $ @ V%$ @-< 0 - dBP , H P X$ @ 8 ( : @ߦ $ V%$ @-< X - dB , 0 H P 8 ( : @ߦ $ @ V% - @-$ < X< dB 6 # 8 6 , 0f H$ Pf 8f ( : @ߦ $ V%$ @-< 0 - dBH , H P X 8 ( : @ߦ $ V% - 0 @- < dB $ , H P X 8 ( : @ߦ $ V% - 0 @- $ < dB , H P X 8 ( : @ߦ < V% - @- < dBh , 0 H P X 8 ( : @ߦ < V% - @- < dB , 0 H P X 8 ( : @ߦ - V% @- < @ < ,dB8 0 H P X 8 ( : @ߦ < V% - @- < dB , 0 H P X 8 ( : @ߦ < V% - @- < dB , 0< H P X 8 ( : @ߦ $ V% - 0 @- < dB $ , H P X 8 ( : @ߦ $ V% - 0 @- < < dB@ , H P X 8 ( : @ߦ < V% - @- < dB , 0 H P X 8 ( : @ߦ < V% - @- < dBh - , 0$ H P X 8 ( : @ߦ $ V% - 0 @- $ < dB , H P X 8 ( : @ߦ $ V% - @- < dB( , 0 H P X 8 ( : @ߦ $ U% - @- < dB` , 0 H P X 8 ( : @ߦ - U% @- < < ,dB 0 H P X 8 ( : @ߦ < U% - @- < dBX , 0 H P X 8 ( : @ߦ < @ U% - @- < dB , 0< H P X 8 ( : @ߦ $ U% - 0 @- < dB $ , H P X 8 ( : @ߦ $ U% - 0 @- < < dB( , H P< X6s 8 (6s C : @ߦ xߣ U% @-< $ < - dBx `- @- , 0 H P X 8 ( : @<< 4 # U% 48 @8-ߣ 4 $ 6 04 <d -dBȯ d d d d d , H P X 8 ( : @ߧ < ߣ -ߦ ߥ G% @8- $ 0< dB , H P X 8 ( : @ߧ $ ߦ -ߣ ߥ G% @8-<< 0dB , H P X 8 ( : @ߧ $ ߣ - 0 G% @(- $ < ,dBX H P X 8 ( : @ߥ $ ߣ $ - E% 0 @(- < dB , H P X 8 ( : @ߥ $ ߣ - 0 E% @(- $ < ,dB诣 H P X 8 ( : @ߥ < ߣ $ - E% 0 @(- < dBx , H P X 8 ( : @ߥ $ ߣ - 0 E% @(- < < ,dB H P X 8 ( : @ߥ < @ߣ $ - E% 0 @(- < dBH , H P X 8 ( : @ߥ $ ߣ - 0 E% @(- < < ,dB H P X 8 ( : @ߥ < ߣ $ - E% 0 @(- < dB , H P X 8 ( : @ߥ $ ߣ - 0 E% @(- < < ,dB H P X 8 ( : @ߥ < ߣ $ - E% 0 @(- < dB P , H P X 8 ( : @ߥ $ ߣ - 0 E% @(- < < ,dB H P X 8 ( : @ߥ < ߣ $ 0 - E% @(- < dBx , H P X 8 ( : @ߥ -ߣ E% @-$ $0 < 0dB , H P X 8 ( : @ߣ $ V%$0 @-< 0 - dB8 , H P X 8 ( : @ߣ $ V% - @- $0 0< dBp , H P X 8 ( : @ߣ < V%$0 @-< 0 - dB , H P X 8 ( : @ߣ < V%$ 0 @-< 0 - dBh , H P X 8 ( : @ߣ $0 V% - 0 @- < @ < dB , H P X 8 ( : @ߣ < V%$0 @-< 0 - dB0 , H P X 8 ( : @ߣ < V% - @- $0 0< dB8 , H P X 8 ( : @ߣ < V%$0 @-< 0 - dB , H P X 8 ( : @ߣ < V%$ 0 @-< 0 - dB , H P X 8 ( : @ߣ $0 V% - 0 @- < < dB( , H P X 8 ( : @ߣ < V%$0 @-< - dB
0 , H P X 8 ( : @< -7 # V%ߣ 8 @-7 $ 0<7dB h < 6 x fր 8 ,6 Hf Pf X 8 ( : @<$ <4 # T%ߣ 484 @- 6< $ - 04 dB , H P X 8 ( : @ < 7 # T%ߣ 87 @- << $ 0 - 7 dB f , H Pf X 8f ( : @ߣ $ T%$ @(-$ - ,f H< dB ` 0 P X 8 ( : @ߥ $ ߣ - E% @(- $ 0< dB , H P X 8 ( : @ߥ $ ߣ $ - E% 0 @(- < dB
, H P X 8 ( : @ߥ $ ߣ - E% @(- $ 0< dB
x , H P X 8 ( : @ߥ $ ߣ $ - E% 0 @(- < dB , H P X 8 ( : @ߥ $ ߣ - E% @(- $ 0< dB , H P X 8 ( : @ߥ $ ߣ $ - E% 0 @(- < dB , H P X 8 ( : @ߥ $ ߣ - E% @(- $ 0< dB , H P X 8 ( : @ߥ $ ߣ $ 0 - E% @(- < dB8 , H P X 8 ( : @ߥ $ ߣ - E% @- $ 0< dB , H P X 8 ( : @ߣ $ S%$ @-< 0 - dB , H P X 8 ( : @ߣ $ S%$ @-< 0 - dB8 , H P X 8 ( : @ߣ $ S% - 0 @- $ < dB , H P X 8 ( : @ߣ $ S%$ @-< 0 - dB , H P X 8 ( : @ߣ $ S% - @- $ 0< dB , H P X 8 ( : @ߣ $ S%$ @-< - dB8 0 , H X P 8 ( : @߯ $ S%$ @-< 0 - dB , H P X 8 ( : @߯ $ S% - 0 @- $ < dBX $ , H P X 8 ( : @߯ $ S%$ @-< 0 - dB , H P X 8 ( : @߯ $ S% - @- < dB , 0 H P X 8 ( : @߯ $ S% - @- < dBX , 0 H P X 8 ( : @߯ - S% @- $ < ,dB 0 H P X 8 ( : @߯ $ S% - @- < dB@ , 0 H P X 8 ( : @߯ $ S% - @- < dB , 0 H P X 8 ( : @߯ $ S% - @- < dBX , 0 H P X 8 ( : @߯ $ S% - @- < dB , 0$ H P X 8 ( : @߯ $ S% - 0 @- < dBx < 6 # $ 0 , x H6 P X6 8f ( : @<$04c S%߯ x @-dc $ 8 4c < - 0dB , H P X 8 ( : @<$ 4 R%߯ x @-4$ 0 <<$ $ - d $ dc dB3 , H P X 8 ( : @<<4 # V% >x @-4$ 0 <<$ $ - d $ dc dB3 , H P X 8 ( : @<<4 # V% >x @-4$ 0 <<$ $ - d $ dc dB4X , H P X 8 ( : @<<4 # V% >x @-4$ 0 <<$ $ - d $ dc dB4 , H P X 8 ( : @<<4 # V% >x @-4$ 0 <<$ $ @dc 8 - d $ dB5 , H P< X6s ( : @<6s C4 # V% >x @-4$ 0$ << x <$ $ $ - ,d dB5 H P X 8 ( : @<$ 4 # V% 6x @-4$ 4 0<$ $ , - dƈ dB5 H P X 8 ( : @$ $ T% - @-<4B #$ x$ 04B dB < dB6 , H P X 8 ( : @< $ 7 # T% x @-7$ <$ - 0g $ dB70 , H P X 8 ( : @<$ 4 # T% >x @-4$ , <<$ $ - 0d dB7 H P X 8 ( : @<$ 4 # T% 6x @-4$ 0 4<$ -dƌ $ dB8 , H P X 8 ( : @<$ 4 # T% .x @-4< ,$ -d $ $ dB8 , 0 H P X 8 ( : @<$ 4 # T% .x @-4< ,$ -d $ $ dB9 , 0 H P X 8 ( : @<$ 4 # T% .x @-4< ,$ @ -d $ $ dB9` , 0 H P X 8 ( : @<$ 4 # T% .x @-4< ,$ $ - 0d $ dB9 , H P X 8 ( : @<$ 4 # T% .x @-4< ,$ - d $ $ dB:8 , 0$ H P X 8 ( : @<$ T%4 # @-<4B # .x x44B , $ dB - < 0$ d $ dB;( , H P X 8 ( : @< <7 #4c # Q% x x @-7$ 4c <$ $ , - 0g dc dB;p H P X 8 ( : @<< 4 #7 # Q% >x x @-4$ ,7 < <$ $ H -dg dB< 0< P7 # X x 87 ( : @<$ 4 # Q% 6x @-4$ 0 4<$ $ - ,dƐ gސ dB( H P X 8 ( : @<$ 4 # Q% .x @-4< ,$ - d $ $ dB>x , 0$ H P X 8 ( : @<$ Q%4 # @-<4B # .x x44B , $ dB - < 0$ d $ dB?h , H P X 8 ( : @< <7 #4c # Q% x x @-7$ 4c <$ - 0g dc $ dB? , H P X 8 ( : @<< 4 #7 # Q% >x x @-4$ ,7 < <$ - Hd $ g $ dB@P 0$ P X 8 ( : @<< 4 #7 # Q% >x x @-4$ ,7 < <$ $ - 0d g dB@ < H7 # P x X7 8 (gޔ : @<$ 4 # Q% 6x @-4$ 0 4<$ $ - ,dƔ dBA H P X 8 ( : @<$ 4 # Q% .x @-4< ,$ $ , - d $ dBA 0 H P X 8 ( : @<$ Q%4 # @-<4B # .x x44B , $ @dB$ < , - d dBA 0< H7 # P x X7 8 (gޔ : @$ $ Q%$ @-<4B #$ x - ,4B 0 dB < dBBh H P X 8 ( : @ $ Q%$ @-$ 0<$ - ,g dBB $ H P X 8 ( : @<$ 4 # Q% .x @-4< ,$ - $ ,d HdBC 0 P X 8 ( : @$ $ Q%$ @-<4B # - , x 4B dB < dBC 0 H P X`- 8$ (< : @<f4 # Q% >x @-4$ , << <$ $ $ - 0d dBD f^ - - g H P X 8 ( : @<$ 4 # V% 6x @-4$ 0 4<$ -dƘ $ dBD , H P X 8 ( : @<$ 4 # V% .x @-4< ,$ -d $ $ dBEX , 0 H P X 8 ( : @<$ 4 # V% .x @-4< ,$ -d $ $ dBE , 0 H P X 8 ( : @<$ 4 # V% .x @-4< ,$ @ -d $ $ dBF , 0 H P X 8 ( : @<$ 4 # V% .x @-4< ,$ -d $ $ dBF , 0 H P X 8 ( : @<$ 4 # V% .x @-4< ,$ -d $ $ dBF $ ,6 0 x H6 P X 8 ( : @<<4 #4 # .x >x V%44 @- , <<$ $ -$ d d dBG , 0 H P X 8 ( : @<<4 #4 # .x >x V%44 @- , <<$ $ $ -d d dBH0 , 0 H P X 8 ( : @<<4 #4 # .x >x V%44 @- , <<$ $ $ -d d dBH , 0 H P X 8 ( : @<<4 #4 # .x >x V%44 @- , <<$ $ $ -d d dBI , 0 H P X 8 ( : @<<4 #4 # .x >x V%44 @- , <<$ $ $ -d d dBI , 0 H P X 8 ( : @<<4 #4 # .x >x V%44 @- , <<$ $ $ -d d dBJ , 0 H P X 8 ( : @<<4 #4 # .x >x V%44 @- , <<$ $ @$ -d d dBJ` , 0 H P X 8 ( : @<<4 #4 # .x >x V%44 @- , <<$ $ $ -d d dBJ , 0 H P X 8 ( : @<<4 #4 # .x >x V%44 @- , <<$ $ $ ,d 0 - d dBK8 H P X$ 8 < ( : @$ - , V% @(-$ f询 H< dBL( P X 8 ( 0 : @ߥ $ ,$ H - E% P$ @(- X$ 8 | < dBL` ( 0 : @ߥ $ $ H - E% P @(- X$ 8 $ ,< dBL ( 0 : @ߥ $ ,$ H - E% P$ @(- X$ 8 < dBL ( 0 : @ߥ $ $ H - E% P @(- X$ 8 < $ ,< dBM ( 0 : @ߥ $ H$ , - E% P$ @(- X$ 8 | < dBMP ( 0 : @ߥ $ $ , - H E% @(- P$ < XdBM 8 ( 0 : @ߥ $ - , P E% @-< <$ dBMȯ H X 8 ( 0 : @$ $ U%$ @-$ - ,4B x 4B < dBNP H P X 8 ( 0 : @$$ < U%4 @- ?x<$ - 4 $ dBN , H P X 8 ( 0 : @$$ , < U%44 @- /x ?x<$ -$ 4 4 $ dBO , H P X 8 ( 0 : @$$ , < U%44 @- /x ?x<$ $ 4 4 $ - dBOX , H P< X6R # 8 (6R 0 8 : @ -$ U%6R @-< dBH fS ( , 0 H P X 8 : @$ $ U% - @-$ 0< X$ $ $ dBO ( , H P 8 : @$ - U%$ @-$ X< $ $ dBP , 0 H P$ 8 ( : @ 8$ U%$ @-< X - $ $ $ dBQ@ < ,6 # 0 H6 E P x (6 : @f$ U%$ @-$ $ ( - H< ,$ XdBR $ < fH 0 P 8 : @$ $ S%$ @-$ ,< 0 - XdBS $ H P 8 ( : @ < S%$ @-$ 0<$ - ,$௦ dBT8 6 # 6 H 8 P6 Xf 8$ ( : @$ $ S%$ @-< - ,$ XdBUx ( 0 H P 8 : @$ $ S%$ @-$ ,< H - XdBV $ 0 P 8 ( : @߸ $ S%$ @-< X$ - dBW0 < 6 # , 8 06 H P6 8f ( : @߸ - S% @- $ $ < (dBXp , H P X 8 0 : @߸ - S% @- < dBY , H P X 8 ( 0 : @߸ $ S%$ @-< - dBZ( < 6 # , 8 H6 P X6 8f ($ 0 - : @߸ - S% 8 @- $ < ( , 0 H P X : @߸ - V% @- < dB[h H P X 8 ( , 0 : @߸ $ V% - @- < dB[ H P X 8 ( , 0 : @߸ $ V% - @- < dB[ H P X 8 ( , 0 : @߸ - V% @- < dB\h < H P X 8 ( , 0 : @߸ $ V% - @- < dB\ H P X 8 ( , 0 : @߸ - V% @- $ < HdB] P X 8 ( , 0 : @߸ $ @ V% - @- < dB^ H P X 8 ( , 0 : @߸ $ V% - @- < dB^ < H6 # P x X6 ) 8 (6 ( , 0 : @߸ - V% P @- H Xf 8f ( , 0 : @߸ < V% - @-< XdB_ f 0 H P 8 ( , : @߸ $ W% - @- < dB_ 0 H P X 8 ( , : @߸ $ W% - @- < dB`0 0 H P X 8 ( , : @߸ - W% @- $ < 0dB` H P X 8 ( , : @߸ $ W% - @- < dBa@ 0 H P X 8 ( , : @߸ $ W% - @- < dBa 0 H P X 8 ( , : @߸ $ @ W% - @- < dBb` 0 H P X 8 ( , : @߸ $ W% - @- < dBb 0 H P X$ 8 ( , : @߸ < W% - X @- < dBcp $ 0 H P 8 ( , : @߸ $ W% < @-< X< -dBc 0 H P 8 ( , : @߸ $ W% | @-< `- -< dBd0 0 H P X 8 ( , : @߸ $ W%< @-< X -dBdp `- 0 H P - 8 ( , : @߸ $ W%$ @-< < X 0 - HdBd `- P 8 ( , : @< - X Q% @- < dBd 0 H P 8 ( , : @ - Q% @- 0< X< HdBg P 8 ( , : @ < Q% - @-< < dBg 06 # H P6 X x 86 ( f ( , : @$ < Q% - @-<fdBh0 H X f P 8 ȯ ( , 0 : @ߣ $ $ - C% @- < X< dBh H P 8 ȯ ( , 0 : @ߣ $ $ < H - X C% $ @- < dBi@ P 8 ȯ ( , 0 : @ߣ $ < - X C% @- $ < HdBi P 8 ȯ ( , 0 : @ߣ $ $ < X - C% @- < dBjP H P 8 ȯ ( , 0 : @ߣ $ $ < H - X C% $ @- < dBj P 8 ȯ ( , 0 : @ߣ $ < - X C% @- $ @ < HdBkp P 8 ȯ ( , 0 : @ߣ $ $ < X - C% @- < dBl H P 8 ȯ ( , 0 : @ߣ $ < $ X - C% $ @- H< dBl < P6 # 8 x 6 + ( ,6 ( 0 : @ߣ $ - H C% @-$ << < XdBm P 8 ( , 0 : @$ < Q% - X @- < HdBm@ P 8 ( , 0 : @$ < Q% - X @- < HdBm P 8 ( , 0 : @$ < Q% - @- H< XdBm f P 8 ( , 0 : @$ < Q% - @- H< XdBn P 8 ( , 0 : @$ - Q% H @- < X< dBp P 8 ( , 0 : @$ < Q% - X @- < dBq f H P 8 ( , 0 : @$ - Q%$ @-< X<f$ dBq@ 0 H P 8 ȯ ( , : @ߣ $ -$ $ C%$ @-<< dBq 0 H P X 8 ȯ ( , : @ߣ $ -$ $ C%$ @-<< dBrP 0 H P X 8 ȯ ( , : @ߣ $ -$ $ C%$ @-<< dBr 0 H P X 8 ȯ ( , : @ߣ $ -$ $ C%$ @-<< dBs` 0 H P X 8 ȯ ( , : @ߣ $ -$ $ C%$ @-<< dBs 0 H P X 8 ȯ ( , : @ߣ $ @ -$ $ C%$ @-<< dBt 0 H P X 8 ȯ ( , : @ߣ $ -$ $ C%$ @-<< dBu 0 H P X 8 ȯ ( , : @ߣ $ < - X$ C%$ @-<$ dBu 0 H P 8 ȯ ( , : @ߣ $ /<$ < C% - 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Tx: %9llu pps (%9llu) (%llu SHORT) (%llu PKI Err) (%llu UNDERRUNS) (%llu COL) Application compiled with: [ DUTY CYCLE ] CPU idle: %d:%3u.%02u%% FPA pools: PKT: %d, WQE: %d, OP: %d Out of memory initializing %s.
Packet Buffers WQ Entries PKO Cmd Buffers Gather List Entries LRO Buffers %s Board Init failed
%s warning, MacAddrInfo init failed
Fau allocation failed
ptr[%d]: 0x%016llx size: %d pool %d
Total Bytes: %d
/var/tmp/13115/liquidio-linux-driver-fwsrc-80eb6bfabf10c84cca6dd66fe57b56c77608818a/octeon/se/apps/nic/cvmcs-nic-main.c cvmx_wqe_get_len(wqe) != 0 mismatch wqe bpid %d port bpid %d
mismatch iq num %d wqe bpid %d iq_num bpid %d
[ DRV ] failed to allocate rsp wqe.
VF with ifidx %u is trusted
VF with ifidx %u is not trusted
ERROR: cvmcs_alloc_or_find_rss_state_array failed
ERROR: Firmware dump initialization failed
ERROR: mbcast_list initialization failed
__per_core_stats version: %s %s build time: %s
1.7.2 131- 2018-03-06 17:11:21 console verbose nqm_vf_mode= sata_only_map nqm_sq_credits= intr_coalesce_off nqm_cplq_size= SDK %s (%s)
3.1.2-p12-L3, build 603 Development Build %s Mar 6 2018 ERROR: failed to alloc per_core_stats array
Global initialization of components is failed
? ? @ @ @ @p @` @P @@ @0 ? B B ? B B B ? ? A A ? ? A ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? A Ax A @ @cvmcs_nic_init_global cvmcs_nic_send_to_pko cannot add, port exists
GMX%d: Adding VNIC %d to IPD %d MAC %012lx gmx_offset %d
GMX%d: ifidx=%d Failed to add MAC %012lx!
mcast_hash_%d %s Allocation failed for hash_table
%s: Error allocating vnic_mcast_lut
mcast_freelist_%d %s: Error allocating vnic_mcast_free
cannot del, port does not exist
__mac_meminfo __octnic %s Allocation failed for octnic
Swordfish - 4 port Swordfish - 2 port NIC COPPERHEAD Unknown (board_type: %d) boardtype: %s
Board type: %s
%s: No active ports found
GMX%d MAC %012lX
First MBUF size: %u
Subsequent MBUF size: %u
loop interface port number %d
ERROR: %s qpg entry alloc failed
ERROR: %s BP ID allocation failed
port%d_chan%d_aura ERROR: %s AURA %d alloc failed
setting bpid-%d on xport.port-%d chan-%d aura-%d
# cvmcs: Failed to initialize input ports
S R O O O O S O O O O O O O O O O R O O O O O O O O O O Rt O O O O Q O O P4 O O O O Q O O O Qadd_port_to_nic hash_table_alloc cvmcs_nic_init_board_info cvmcs_nic_init_ptp cvmcs_nic_init_gmx_packet_io %.*s ifidx %d Port %d: %d Mbps %s duplex %s
Full Half UP DOWN WARNING: there are still %lu buffers left in AURA-%d of ifidx-%d, txpciq-%d at the time of queue cleanup
[ DRV ] Failed to send OPCODE_NIC_VF_DRV_NOTICE!!!
Speed: 10base_tx_half Speed: 10base_tx_full Speed: 100base_tx_half Speed: 100base_tx_full Speed: 1000base_tx_half Speed: 1000base_tx_full %s: PHY address invalid for port %d
ifidx:%d Not sending NIC_INFO because interface is not up
ifidx:%d Failed to alloc link_info!!!
ifidx:%d Sending NIC_INFO (OQ: %d link: %s st: %lx)
Failed to send NIC_INFO
clear at linkup latched_ber=%d ber_cnt=%d err_blks=%d for ipd_port %d
error setting more than %d mac address not supported
%s: not found
GMX%d: No space in MAC hashtable for port %d MAC %012lx
Tried to add mac %012lx to entry %d which already had mac %012lx, overriding
Deleting MAC for interface %d at index %d gmx_offset %d hash_idx %d
GMX%d: [%d] Mismatch trying to remove MAC %012lx
%s MAC filter for VNIC %d GMX%d interface %d at index %d gmx_offset %d
Enabling Disabling Max MTU for Host interface %d is set to %d
Error: Interface-%d MTU cannot be set higher than %d
MTU for Host interface %d is set to %d; effective_mtu = %d
Error: interface %d not allowed to change Link MTU. Only controller interface can change link MTU
MTU must be between %d and %d.
interface %d port %d: MTU changed to %d
%s: Only OCTEON3 required. %s: Error: timer %d out of range
Port:%d Couldnt get info about PHY
PHY address invalid for port %d
cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d TIME OUT(data)
cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d INVALID READ
cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d TIME OUT(address)
[ DRV ] failed to allocate timestamp return buffer.
Got Timestamp %016llu rptr.s.addr=%016llu size=%d
%s : autoneg = %s phy = %s pause = %s interface is %d index is %d
ON OFF Writing advertisement register in 1000 base-x mode
Writing advertisement register in SGMII-PHY mode
Writing Half Duplex in advertisement register
Writing Full Duplex in advertisement register
Error: Unknown Value For Duplex Mode While Writing Advertisement Register
Writing Speed 10Mbps in advertisement register
Writing Speed 100Mbps in advertisement register
Writing Speed 1000Mbps in advertisement register
Error: Unknown Value For Speed While Writing Advertisement Register
Advertisement Register Is Sent to External PHY Chip
Error Setting Unknown Speed for GMX in Autoneg ON Condition
Error: Unknown Speed Setting Received From Host For Autoneg OFF Condition
Error: Unknown Duplex Setting Received From Host For Autoneg OFF Condition
SGMII%d: Timeout waiting for port %d to finish reset
Writing %x @ %x for phy_addr %x on page %d
Read val 0x%lx at page 0x%x_0x%x for phy addr 0x%x
too many iqs numqs %d numfree %d
too many oqs or numqs %d numfree %d
PCI port %d:
%d: IQ%02d mask 0x%016lx
too many iqs numqs %d numfree %d
too many oqs numqs %d numfree %d
too many iqs
too many oqs
firmware controlled allocation
host controlled allocation
port%d_aura PF = %d VF = %d is not provisioned
ERROR: %s ctrl_qpg entry alloc failed
BPID of BGX port-%d is %u
ifidx %d : Port does not exist
Out of mcast entries
[ DRV ] Cannot use packet pool buf for sending link info
[ DRV ] failed to allocate mdio_info return buffer.
[ DRV ] prepare mdio info pkt failed
[ DRV ] prepare link info pkt failed
[ DRV ]: cvm_free_host_instr: NULL WQE nic_if_cfg: GMX%u: Host requested %lu IQs and %lu OQs (base_queue auto-select)
(Host requested base queue %d).
ifidx=0x%x already configured
error ifidx confg
port %d iq num %d pkind %d,bpkind %d bpid %d fau %d
error configuring dpi Backpressure
rptr. size %d
Sending cfg resp ifidx %d iqmask 0x%016lx oqmask 0x%016lx
npu interface identification failed
iq num %d pkind %d, bpid %d fau %d
fau alloc failed
GMX%d: IPD %d pkind %d, bpid %d fau %d
%s: Invalid ifidx (%d) received in command
%s: GMX Port at ifidx (%d) appears inactive
Command for RX Control: (ifidx %d Command: %s)
Start Stop Command to change MTU (ifidx %d gmxport: %d new_mtu %d)
Command to change MAC Addr (ifidx %d port %d MAC 0x%lx [%d])
GMX%d: ifidx=%d Failed to add MAC %012lx
GMX%d: ifidx=%d MAC changed to %012lx
Command to set multicast MAC Addr list and Flags (ifidx %d port %d Flags 0x%lx-->0x%lx size %d)
ERROR: MAC Addr list size exceeded max size %d
Command to change Flags (ifidx %d port %d Flags 0x%lx-->0x%lx)
Command to clear NIC stats(ifidx %d port %d)
Command to change nic Settings
Command to ADD VxLAN Port %d ifidx %d
VxLAN Port is added in DB octnic->port[%d].vxlan_default_ports %d
Adding VxLAN Port in DB operation is failed %d
Command to DELETE VxLAN Port %d ifidx %d
VxLAN Port is deleted from DB octnic->port[%d].vxlan_default_ports %d
Deleting VxLAN Port %x from DB operation is failed %d
Unknown NIC Command 0x%08x
%s: ERROR reserving L1 SQ
ERROR: %s:PQ/L1 queue configuration
%s: allocated L1-SQ%d and connected to NULL link, to use for DQ flush
%s: SQX_CHANNEL[hw_xoff] for L2-SQ-%d is clear; Nothing to do
__oq_status __dq_flush_in_progress Failed to setup SQ pair to flush a stuck DQ
Error: PKO-DQ's of BGX-%d were not flushed even after 100msec, proceeding with link down anyway
Error CVMX_BGX%d_CMR%d_RX_FIFO_LEN not zero, proceeding with link down anyway
Error CVMX_BGX%d_CMR%d_TX_FIFO_LEN not zero, proceeding with link down anyway
enable_fec0 enable_fec1 Failed to set environment variable.
%s: enable_fec0=%d
%s: enable_fec0 default setting is off
octeth0_speed %s: octeth0_speed=%d
%s: octeth0_speed default setting is 25
octeth1_speed %s: octeth1_speed=%d
Failed to set environment variable, enable_fec0. ret=%d
Failed to set environment variable: enable_fec1. ret=%d.
%s: unknow ncmd->s.cmd=%x
0 < X 8 p X 0 \ < ( " #0 pcvmcs_nic_change_phy_settings cvmcs_find_free_mac_hash_idx cvmcs_nic_change_link_mtu cvmx_gpio_cfg_sel cvmx_gpio_set_freq cvmcs_nic_change_settings cvmcs_do_mdio_read_write cvmcs_nic_cfg_ioqueues_cn78xx cvmcs_nic_cfg_ioqueues_cn73xx cvmcs_nic_process_cmd cvmcs_nic_setup_flush_dq cvmcs_nic_flush_dq cvmcs_nic_uboot_ctl %s: error invalid group number
%s: sso high threshold
%s: sso low threshold
%s: error invalid threshold value
Error: unknown FLR BH continuation event %u
Error: FLR duration %uus exceeded maximum
cvmx_tim_add_entry: Tried to schedule work too far away. cvmx_tim_add_entry: Tried to schedule work too soon. Delaying it. cvmx_tim_add_entry: Failed to allocate memory for new chunk. FLR timer add failed
%s: cvmx_fpa_alloc failed; cannot schedule bottom half
SLI_MAC0_PF0_FLR_VF_INT is 0. I don't know which VF did an FLR.
SLI_MAC0_PF1_FLR_VF_INT is 0. I don't know which VF did an FLR.
Error: UNKNOWN FLR BH event! (0x%x)
Found PF0/1 STOPREQ set (0x%x); clearing...
---- Dumping CN73xx DPI registers
%s[0x%016lx]: 0x%016lx
DPI Error: CVMX_BGX2_SPU000_INT[%llx][%u] Error: CVMX_BGX2_SPU001_INT[%llx][%u] Error: CVMX_BGX2_SPU002_INT[%llx][%u] cn73xx_sso_intr_handler cn73xx_schedule_flr_intr_handler_bh Error port :%d queue: %d
PACKET SEND FAILED : %d
protocol header alloc failed
Gather list alloc failed
[%s]ERROR: RX STATE IS OFF
[%s]ERROR: PORT/QUEUE = -1
[%s]ERROR: SEND TO PKO FAILED
ERROR: LRO context allocation failed; max LRO buffer limit reached.
ERROR: LRO context allocation failed; max LRO context limit reached.
ERR : LRO CONTEXT ALLOC FAILED
ERR: GATHER LIST ALLOC FAILED
too many segs
timer_work alloc failed
timer add failed
TIMER SETTING ERROR
__lro_hash_table ERROR: failed to alloc lro_hash_table
cvmcs_nic_flush_lro Invalid queue for Loop back
too many bufs
%s: ERROR: Internal error
__cvmx_pko3_lmtdma __mbcast_list
****CORE %d WATCHDOG TIMER EXPIRED****
****REGISTER DUMP OF CORE %d****
****REGISTER DUMP OF CORE %d****
%3s ($%02d): 0x%08x%08x %3s ($%02d): 0x%08x%08x
%.16s: 0x%08x%08x
COP0_CAUSE COP0_CAUSE 0x%016lx %s
Reserved exception cause COP0_STATUS COP0_STATUS 0x%016lx
COP0_BADVADDR COP0_BADVADDR 0x%016lx
COP0_EPC COP0_EPC 0x%016lx
***CALL TRACE OF CORE %d***
#%2d %p
******************************************************************
va=%0*lx size=%d asid=%02x
[pa=%0*lx c=%d d=%d v=%d g=%d] [pa=%0*lx c=%d d=%d v=%d g=%d]
Core %d: Unhandled Exception. See oct-fwdump for details.
Core %d: watchdog timer expired. See oct-fwdump for details.
__nic_fwdump_block __nic_fwdump_ctx BOOT LOG OFFSER %d
r0 at v0 v1 a0 a1 a2 a3 t0 t1 t2 t3 t4 t5 t6 t7 s0 s1 s2 s3 s4 s5 s6 s7 t8 t9 k0 k1 gp sp s8 ra Interrupt TLB modification tlb load/fetch tlb store address exc, load/fetch address exc, store bus error, instruction fetch bus error, load/store syscall breakpoint reserved instruction cop unusable arithmetic overflow trap floating point exc cop2 exception mdmx unusable watch machine check cache error p 0 P X h p 0__rss_state U-Boot_SE_API UBootAPI %s: Calling syscall at 0x%p, sig addr: 0x%lx
%s: sdi_addr: 0x%lx, type: %p, sdi: %p
%s: Calling syscall(%lx, %d, %d, 0x%lx, 0x%lx, 0x%lx, 0x%lx)
%s: ret: %d
%s: Calling syscall(%lx, %d, %d, 0x%lx, 0x%lx, 0x%lx, %lx)
%s: Calling syscall(%lx, %d, %d, 0x%lx, 0x%lx, 0x%lx, 0x%x, 0x%lx)
Error getting U-Boot SEAPI handle Could not get environment variable "%s"
error unable to alloc buffer Error getting version information Failed to set "%s"
Failed to save the environment uboot_seapi_dev_open_storage uboot_seapi_dev_close_storage uboot_seapi_dev_enum_storage uboot_seapi_dev_read uboot_seapi_dev_write uboot_seapi_dev_file_read ERROR: cvmx_pko_queue_static_config() failed ERROR: %s empty group mask disables work on core# %llu, ignored.
core %d shutdown old app requested
%u cores are now running the new app
core %d unplug from old app requested
# cvmcs: cvmcs_shutdown() called... # cvmcs: cvmcs_shutdown() completed. PKO%d: %10u pps (%10u) db: %8llu
Total SSO packet count %lu
L2C: Hits/sec: %llu Hit:%3u.%02u%% Victim:%3u.%02u%% NoAlloc: %3u.%02u%%
Cores: %llu MHz (boot: %d, disp: %d, ctrl: %d), %s app
cvmx-app-hotplug-block __live_upgrade_ctx %u cores are running the new app
cvmx_pow_set_group_mask [ DRV ] Active PCI Queues: %d (derived from checking queue registers)
[ DRV ] PCIPKOMAP (port, queue):
%3d: (%3d, %3d) [ DRV ] Core driver PKO is in state (0x%x); PKO Send abort!
[ DRV ] Unsupported configuration: total_bytes: %d segs: %d
[ DRV ] total_bytes cannot be > 65528; segs cannot be > 63 [ DRV ] %s: OQ# %d is not active
[ DRV ] CVM_PKO: Allocation failed in sending PKO data cvm_send_pci_pko_direct __oct [ DRV ] octeon device alloc failed [ DRV ] DMA Queue initialization failed CVMX_BOARD_TYPE_NULL CVMX_BOARD_TYPE_SIM CVMX_BOARD_TYPE_EBT3000 CVMX_BOARD_TYPE_KODAMA CVMX_BOARD_TYPE_NIAGARA CVMX_BOARD_TYPE_NAC38 CVMX_BOARD_TYPE_THUNDER CVMX_BOARD_TYPE_TRANTOR CVMX_BOARD_TYPE_EBH3000 CVMX_BOARD_TYPE_EBH3100 CVMX_BOARD_TYPE_HIKARI CVMX_BOARD_TYPE_CN3010_EVB_HS5 CVMX_BOARD_TYPE_CN3005_EVB_HS5 CVMX_BOARD_TYPE_KBP CVMX_BOARD_TYPE_CN3020_EVB_HS5 CVMX_BOARD_TYPE_EBT5800 CVMX_BOARD_TYPE_NICPRO2 CVMX_BOARD_TYPE_EBH5600 CVMX_BOARD_TYPE_EBH5601 CVMX_BOARD_TYPE_EBH5200 CVMX_BOARD_TYPE_BBGW_REF CVMX_BOARD_TYPE_NIC_XLE_4G CVMX_BOARD_TYPE_EBT5600 CVMX_BOARD_TYPE_EBH5201 CVMX_BOARD_TYPE_EBT5200 CVMX_BOARD_TYPE_CB5600 CVMX_BOARD_TYPE_CB5601 CVMX_BOARD_TYPE_CB5200 CVMX_BOARD_TYPE_GENERIC CVMX_BOARD_TYPE_EBH5610 CVMX_BOARD_TYPE_LANAI2_A CVMX_BOARD_TYPE_LANAI2_U CVMX_BOARD_TYPE_EBB5600 CVMX_BOARD_TYPE_EBB6300 CVMX_BOARD_TYPE_NIC_XLE_10G CVMX_BOARD_TYPE_LANAI2_G CVMX_BOARD_TYPE_EBT5810 CVMX_BOARD_TYPE_NIC10E CVMX_BOARD_TYPE_EP6300C CVMX_BOARD_TYPE_EBB6800 CVMX_BOARD_TYPE_NIC4E CVMX_BOARD_TYPE_NIC2E CVMX_BOARD_TYPE_EBB6600 CVMX_BOARD_TYPE_REDWING CVMX_BOARD_TYPE_NIC68_4 CVMX_BOARD_TYPE_NIC10E_66 CVMX_BOARD_TYPE_EBB6100 CVMX_BOARD_TYPE_EVB7100 CVMX_BOARD_TYPE_SFF6100 CVMX_BOARD_TYPE_NIC4E_66 CVMX_BOARD_TYPE_SNIC10E CVMX_BOARD_TYPE_SNIC10E_61 CVMX_BOARD_TYPE_IW_EVB CVMX_BOARD_TYPE_CNF71XX_REF CVMX_BOARD_TYPE_MOONSHOT CVMX_BOARD_TYPE_EVB7000 CVMX_BOARD_TYPE_EVB7000_SFF CVMX_BOARD_TYPE_NAS7000_REF CVMX_BOARD_TYPE_EAP7000_REF CVMX_BOARD_TYPE_ROUTER7000_REF CVMX_BOARD_TYPE_EBB7800 CVMX_BOARD_TYPE_NIC401NVG CVMX_BOARD_TYPE_NIC210NVG CVMX_BOARD_TYPE_SFF7000 CVMX_BOARD_TYPE_EBB7800_CFG1 CVMX_BOARD_TYPE_TB7600 CVMX_BOARD_TYPE_EBB7804 CVMX_BOARD_TYPE_EBB7804_CFG1 CVMX_BOARD_TYPE_TB7000 CVMX_BOARD_TYPE_EBB7800_CFG0 CVMX_BOARD_TYPE_EBB7804_CFG0 CVMX_BOARD_TYPE_SWORDFISH CVMX_BOARD_TYPE_SFF7800 CVMX_BOARD_TYPE_WAVE2 CVMX_BOARD_TYPE_NIAGARA83X CVMX_BOARD_TYPE_EBB7304 CVMX_BOARD_TYPE_NIC73 CVMX_BOARD_TYPE_NIC25E CVMX_BOARD_TYPE_NIC225E CVMX_BOARD_TYPE_EBB7504 CVMX_BOARD_TYPE_RAINIER CVMX_BOARD_TYPE_NIC125E CVMX_BOARD_TYPE_NICX40E CVMX_BOARD_TYPE_NIC23 CVMX_BOARD_TYPE_EBB7500 CVMX_BOARD_TYPE_COPPERHEAD CVMX_BOARD_TYPE_MAX CVMX_BOARD_TYPE_CUST_DEFINED_MIN CVMX_BOARD_TYPE_CUST_WSX16 CVMX_BOARD_TYPE_CUST_NS0216 CVMX_BOARD_TYPE_CUST_NB5 CVMX_BOARD_TYPE_CUST_WMR500 CVMX_BOARD_TYPE_CUST_ITB101 CVMX_BOARD_TYPE_CUST_NTE102 CVMX_BOARD_TYPE_CUST_AGS103 CVMX_BOARD_TYPE_CUST_GST104 CVMX_BOARD_TYPE_CUST_GCT105 CVMX_BOARD_TYPE_CUST_AGS106 CVMX_BOARD_TYPE_CUST_SGM107 CVMX_BOARD_TYPE_CUST_GCT108 CVMX_BOARD_TYPE_CUST_AGS109 CVMX_BOARD_TYPE_CUST_GCT110 CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX CVMX_BOARD_TYPE_CUST_L2_ZINWELL CVMX_BOARD_TYPE_CUST_DEFINED_MAX CVMX_BOARD_TYPE_CUST_PRIVATE_MIN CVMX_BOARD_TYPE_UBNT_E100 CVMX_BOARD_TYPE_CUST_CLARK CVMX_BOARD_TYPE_CUST_PRIVATE_MAX CVMX_BOARD_TYPE_MODULE_MIN CVMX_BOARD_TYPE_MODULE_PCIE_RC_4X CVMX_BOARD_TYPE_MODULE_PCIE_EP_4X CVMX_BOARD_TYPE_MODULE_SGMII_MARVEL CVMX_BOARD_TYPE_MODULE_SFPPLUS_BCM CVMX_BOARD_TYPE_MODULE_SRIO CVMX_BOARD_TYPE_MODULE_EBB5600_QLM0 CVMX_BOARD_TYPE_MODULE_EBB5600_QLM1 CVMX_BOARD_TYPE_MODULE_EBB5600_QLM2 CVMX_BOARD_TYPE_MODULE_EBB5600_QLM3 CVMX_BOARD_TYPE_MODULE_MAX Unsupported Board
[ DRV ] CRITICAL ERROR!!! [ DRV ] Failed to send core driver indicator!!!!
Disabling NP_DAT NP_SOP & NP_EOP for 56xx Pass2 [ DRV ] Unsupported Opcode: %x in instruction
[ DRV ] OPCODE %x is not the supported range. Registration failed
Read %x from %lx into %p
---- Dumping data for CN68xx SLI DebugSelect DbgSelect: %x DbgValue: 0x%08x
---- Dumping CN68xx PEM registers for PCIe port %d
Invalid pcie port %d passed to %s
PEM
---- Dumping CN68xx FPA registers FPA
---- Dumping CN68xx PIP registers PIP
---- Dumping CN68xx IPD registers IPD Only first 8 qos counters are printed below
---- Dumping CN68xx PCIe port %d config registers
Port%d Config[0x%x]: 0x%08x
---------Begin CN68xx regs dump ----------- SCRATCH: 0x%016lx
PIP Stats for port %x
Packets: %lu
Raw Packets: %lu
Dropped Packets: %lu
Pkind %d config:
PIP_PRT_CFG[%d]: 0x%016lx
PIP_PRT_TAG[%d]: 0x%016lx
PIP_PRT_CFGB[%d]: 0x%016lx
SLI_CTL_PORT0: 0x%016lx
SLI_CTL_PORT1: 0x%016lx
SLI_CTL_STATUS: 0x%016lx
SLI_DATA_OUT_CNT: 0x%016lx
SLI_INT_ENB_CIU: 0x%016lx
SLI_INT_ENB_PORT0: 0x%016lx
SLI_INT_SUM: 0x%016lx
SLI_PKT0_CNTS: 0x%016lx
SLI_PKT1_CNTS: 0x%016lx
SLI_PKT2_CNTS: 0x%016lx
SLI_PKT3_CNTS: 0x%016lx
SLI_PKT0_INSTR_BADDR: 0x%016lx
SLI_PKT1_INSTR_BADDR: 0x%016lx
SLI_PKT2_INSTR_BADDR: 0x%016lx
SLI_PKT3_INSTR_BADDR: 0x%016lx
SLI_PKT0_INSTR_BAOFF_DBELL: 0x%016lx
SLI_PKT1_INSTR_BAOFF_DBELL: 0x%016lx
SLI_PKT2_INSTR_BAOFF_DBELL: 0x%016lx
SLI_PKT3_INSTR_BAOFF_DBELL: 0x%016lx
SLI_PKT0_INSTR_FIFO_RSIZE: 0x%016lx
SLI_PKT1_INSTR_FIFO_RSIZE: 0x%016lx
SLI_PKT2_INSTR_FIFO_RSIZE: 0x%016lx
SLI_PKT3_INSTR_FIFO_RSIZE: 0x%016lx
SLI_PKT0_INSTR_HEADER: 0x%016lx
SLI_PKT1_INSTR_HEADER: 0x%016lx
SLI_PKT2_INSTR_HEADER: 0x%016lx
SLI_PKT3_INSTR_HEADER: 0x%016lx
SLI_PKT0_OUT_SIZE: 0x%016lx
SLI_PKT1_OUT_SIZE: 0x%016lx
SLI_PKT2_OUT_SIZE: 0x%016lx
SLI_PKT3_OUT_SIZE: 0x%016lx
SLI_PKT0_SLIST_BADDR: 0x%016lx
SLI_PKT1_SLIST_BADDR: 0x%016lx
SLI_PKT2_SLIST_BADDR: 0x%016lx
SLI_PKT3_SLIST_BADDR: 0x%016lx
SLI_PKT0_SLIST_BAOFF_DBELL: 0x%016lx
SLI_PKT1_SLIST_BAOFF_DBELL: 0x%016lx
SLI_PKT2_SLIST_BAOFF_DBELL: 0x%016lx
SLI_PKT3_SLIST_BAOFF_DBELL: 0x%016lx
SLI_PKT0_SLIST_FIFO_RSIZE: 0x%016lx
SLI_PKT1_SLIST_FIFO_RSIZE: 0x%016lx
SLI_PKT2_SLIST_FIFO_RSIZE: 0x%016lx
SLI_PKT3_SLIST_FIFO_RSIZE: 0x%016lx
SLI_PKT_CNT_INT: 0x%016lx
SLI_PKT_CNT_INT_ENB: 0x%016lx
SLI_PKT_CTL: 0x%016lx
SLI_PKT_DATA_OUT_ES: 0x%016lx
SLI_PKT_DATA_OUT_NS: 0x%016lx
SLI_PKT_DATA_OUT_ROR: 0x%016lx
SLI_PKT_DPADDR: 0x%016lx
SLI_PKT_IN_DONE0_CNTS: 0x%016lx
SLI_PKT_IN_DONE1_CNTS: 0x%016lx
SLI_PKT_IN_DONE2_CNTS: 0x%016lx
SLI_PKT_IN_DONE3_CNTS: 0x%016lx
SLI_PKT_IN_INSTR_COUNTS: 0x%016lx
SLI_PKT_IN_PCIE_PORT: 0x%016lx
SLI_PKT_INPUT_CONTROL: 0x%016lx
SLI_PKT_INSTR_ENB: 0x%016lx
SLI_PKT_INSTR_RD_SIZE: 0x%016lx
SLI_PKT_INSTR_SIZE: 0x%016lx
SLI_PKT_INT_LEVELS: 0x%016lx
SLI_PKT_IPTR: 0x%016lx
SLI_PKT_OUT_BMODE: 0x%016lx
SLI_PKT_OUT_BP_EN: 0x%016lx
SLI_PKT_OUT_ENB: 0x%016lx
SLI_PKT_OUTPUT_WMARK: 0x%016lx
SLI_PKT_PCIE_PORT: 0x%016lx
SLI_PKT_PORT_IN_RST: 0x%016lx
SLI_PKT_SLIST_ES: 0x%016lx
SLI_PKT_SLIST_NS: 0x%016lx
SLI_PKT_SLIST_ROR: 0x%016lx
SLI_PKT_TIME_INT: 0x%016lx
SLI_PKT_TIME_INT_ENB: 0x%016lx
SLI_PORT0_PKIND: 0x%016lx
SLI_PORT1_PKIND: 0x%016lx
SLI_PORT2_PKIND: 0x%016lx
SLI_PORT3_PKIND: 0x%016lx
SLI_TX_PIPE: 0x%016lx
------------------------------------------- dump_cn68xx_pem_regs [ DRV ] DMA: Invalid Remote address: 0x%016llx or size: %d : NULL Address : Zero-byte size field lptr[0x%016lx]: 0x%016lx
rptr[0x%016lx]: 0x%016lx
[ DRV ] DMA: Invalid local address: 0x%016llx : I-bit set for non-OUTBOUND traffic : Little Endian mode %s Invalid DMA Pointer count (local: 0x%016x remote: 0x%016x)
[ DRV ] %s: local size (%u) != remote size (%u)
[ DRV ]: Found PCI-E DMA Command with q_no: %d (Max: %d)
[ DRV ] %s: first size (%u) != last size (%u)
: Reserved field set DMAHdr: 0x%016llx
Dir: %s Fport: %d Lport: %d Counter: %d CntrAdd: %s; wqe @ %lx
Yes No PtrCount -> remote: %d local: %d (fi: %d ii: %d fl: %d)
Printing %d dma chunk words in buf @%p
Printing DMA chunk buf : %p
chunk_size : %d
current_word : %d
max_words : %d
pool : %d
chunk_buf[%d]: 0x%016llx
%s Invalid queue number (%d)
%s DMA Engine %d is not in idle state
DMA Queues 0-%d initialized
comp_ptr_pool Invalid DMA_COMP_PTR %p returned
[ DRV ] CVM_PCI_DMA:Cannot allocate chunk from pool [ DRV ] CVM_PCI_DMA: Warning! Next Chunk Pointer was empty [ DRV ] CVM_PCI_DMA: Warning! Retry failed! Next Chunk Pointer is NULL [ DRV ] ERROR!! %d words were consumed in DMA chunk with %d words
[ DRV ] CVM_PCI_DMA: PCI Write Fail. No DMA chunk [ DRV ] Core driver is in state (0x%x); DMA Send abort!
[ DRV ] %s: Invalid Direction (0x%x) in cmd->flags
error %d is not a valid DPI ring number
cvm_drv_debug_print_dmaq cvm_dma_sdk_chip_specific_setup cvm_post_pcie_dma_command cvm_post_pci_dma_command cvm_pcie_dma_internal cvm_post_pcie_dma_command_o3 cvm_pcie_dma_internal_o3 cvm_pcie_dma_external_o3 cvm_pcie_dma_external --- Printing %d bytes at %p
%02x << %d - %d
------ PRINT WQE @ %p------
swp: unused: 0x%x tag: 0x%x, tt: 0x%x iprt: 0x%x
wqe->pkt_ptr: 0x%016llx (addr: 0x%llx size: %d)
segs: %d len: %d
WQE Header - 4 64-bit Words WQE Data Payload - first 64 bytes WQE Packet Ptr - first %d bytes
------ PRINT WQE @ %p DONE------
Invalid [ DRV ]: Reached maximum allowed debug functions Ordered Atomic Null Null-Null
Bh
Bp
Bx
Bidle-core-loop Named block(%s) is not created
ERROR: Application is not registered for hotplug! WARNING: Hotplug requested on core %d when not all app cores have activated hotplug
Application coremask:
Hotplug coremask: ERROR: Hotplug info region is not setup ERROR: Hotplug info region is invalid %s: timeout waiting for hotplug info
ERROR: Cores-removed callback has not been registered ERROR: Unplug callback has not been registered ERROR: Shutdown callback has not been registered %s: hotplug info %d not valid
%s: empty coremask
ERROR: Failed to get hotplug info for coremask: ERROR: cmvx_app_hotplug_register() failed
ERROR: Failed to get hotplug info for app at index=%d
ERROR: Failed to get hotplug info for coremask
ERROR: Target application has not registered for hotplug!
ERROR: Not all application cores have activated hotplug
ERROR: Not all cores requested are a part of the app r:
ERROR: Trying to remove all cores in app. r: cvmx_app_hotplug_activate cvmx_app_hotplug_get_index ERROR: Incompatible bootmem descriptor version: %d.%d at addr: 0x%llx
ERROR: %s: bad free list ent: %#llx, next: %#llx
ERROR: %s: internal error - addr %#llx %#llx size %#llx %#llx
Printing bootmem block list, descriptor: 0x%llx, head is 0x%llx
Descriptor version: %d.%d
Warning: Bootmem descriptor version is newer than expected mem list is empty! Block address: 0x%08llx, size: 0x%08llx, next: 0x%08llx
List of currently allocated named bootmem blocks: Name: %s, address: 0x%08llx, size: 0x%08llx, index: %d
No named bootmem blocks exist. ERROR: no memory for cvmx_bootmem descriptor provided ERROR: requested memory size too large, truncating to maximum size FATAL ERROR: unable to allocate memory for bootmem descriptor! __cvmx_bootmem_reserved %.32s_%012llx_%u %s: Failed to reserve 0x%llx bytes at address 0x%llx
cvmx_bootmem_phy_alloc cvmx_bootmem_reserve_memory cvmx_clock_get_rate: Unknown clock type %d
( ( cvmx_cmd_queues __cvmx_cmd_queue_init_state_ptr cvmx_cmd_queue_initialize Queue already initialized with different ERROR: %s: Unable to get named block %s.
ERROR: %s: queue %#x out of range
WARNING: %s: pool_size %d not multiple of 8
ERROR: %s: %s max_depth (%d).
ERROR: %s: %s FPA pool (%u).
ERROR: %s: %s FPA pool size (%u).
ERROR: %s: FPA is not enabled.
ERROR: %s: allocating first buffer.
ERROR: cvmx_cmd_queue_shutdown: Unable to get queue information. ERROR: cvmx_cmd_queue_shutdown: Queue still has data in it. /opt/3.1.2j/OCTEON-SDK-3.1.2-p12-L3-603/executive/cvmx-coremask.c pcm != NULL && !((long)pcm & 3) %s: Error: hex string is empty
%s: Non-hex digit within hexstr
%s: hexstr (%s) is too long
%s: strtou returns w/ EINVAL
%016llx 0x%llx Info: named_block<%s> not found.
__common_bootinfo cvmx_coremask_barrier_sync cvmx_coremask_str2bmp Dma Cmd Buffers ERROR: cvmx_dma_engine_shutdown: Engine not idle. uncorrectable single-bit ERROR: Unknown intsn 0x%x
%d:
Error: single bit ECC error detected %u times at address 0x%016llx
Previous error data: 0x%016llx
Physical address: 0x%016llx
ERROR: %s memory ECC error detected
Total ECC errors: %u
Errors at this address: %u
LMC%d ECC: sec_err:%d ded_err:%d
LMC%d ECC: Failing dimm: %u
LMC%d ECC: Failing rank: %u
LMC%d ECC: Failing bank: %u
LMC%d ECC: Failing row: 0x%x
LMC%d ECC: Failing column: 0x%x
LMC%d ECC: syndrome: 0x%x, bit: %d
LMC%d ECC: Failing Address: 0x%016llx
LMC%d ECC: Failing Data: 0x%016llx
%u ECC errors detected at this bit location and address
Cannot continue due to corrupted memory!
Please reset or power cycle this system!
Store buffer double bit error detected, hanging
FBF double bit error detected, hanging
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
" !
" # $ % & '
8 9 : ; < = > ? 1 0 2 3 4 5 6 7 ( ) * + , - . / ! ERROR: %s: FPA on node#%u is not intialized
ERROR: %sFailed to allocate stack for POOL %u:%u
ERROR: %s: POOL invalid
ERROR: %s: AURA/POOL node mismatch
ERROR; %s: POOL buf_size invalid
ERROR: %s: AURA invalid
ERROR: %s: POOL %u:%u block size %u is not valid
ERROR: %s: POOL %u:%u buffer size mismatch
ERROR: %s: POOL %u:%u out of memory, could not allocate %llu bytes
ERROR: %s: invalid block count %u
ERROR: %s: invalid block size %u
ERROR: %s: POOL %u:%u stack setup failed
ERROR: %s: POOL %u:%u memory fill failed
ERROR: %s: POOL %u:%d not available
WARNING: %s: AURA %u:%u buffer count limit %u reduced to POOL available count %u
ERROR: %s: %s
AURA configuration ERROR: %s: POOL argument invalid
ERROR: %s: AURA %u:%d not available
AURA not available POOL not available invalid block size POOL Stack setup POOL buffer memory ERROR: %s: Failed in %s
ERROR: %s pool %d invalid
ERROR: %s: failed pool %u init
ERROR: %s: failed pool %u memory
WARNING: %s: AURA %u:%u is missing %u buffers
ERROR: %s: Unknowm model
WARNING: %s: POOL %u:%u is missing %lld buffers
WARNING: %s: POOL %u:%d could not be cleaned
ERROR: %s: buffer memory base mismatch
%#llx != %#llx
ERROR: %s: buffer memory size mismatch
ERROR: %s: failed to shutdown AURA
ERROR: %s: failed to shutdown POOL
ERROR: %s: POOL %d not empty, %llu/%llu.
cvmx_fpa_pool cvmx_fpa3_setup_fill_pool cvmx_fpa3_pool_stack_init cvmx_fpa3_pool_populate cvmx_fpa3_aura_cfg cvmx_fpa3_set_aura_for_pool cvmx_fpa3_setup_aura_and_pool cvmx_fpa1_setup_pool cvmx_fpa1_pool_init cvmx_fpa3_shutdown_aura cvmx_fpa3_shutdown_pool cvmx_fpa3_num_auras cvmx_fpa3_shutdown_aura_and_pool cvmx_fpa1_shutdown_pool ERROR: %s: global resource create node=%u
ERROR: %s: node=%u desired aura=%d
ERROR: %s: global resource not created
ERROR: %s: FPA_POOL %d unavailable
cvmx_fpa3_reserve_aura cvmx_fpa3_num_auras cvmx_fpa3_reserve_pool cvmx_fpa3_num_pools cvmx_fpa3_release_pool cvmx_fpa1_reserve_pool Failed to create FAU global resource ERROR: Failed to alloc FAU register of %d bytes
ERROR: Invalid FAU register %d got allocated
ERROR: Invalid address %d in cvmx_fau_free
ERROR Failed to release FPU register %d
cvmx-global-resources ERROR: %s: failed to allocate global resource name block. sz=%d
ERROR: %s: reached global resources limit for %s
ERROR: %s: out of memory %s, size=%d
ERROR: %s: cannot find resource %s
ERROR: cannot find resource %s
ERROR: %s: could not free memory to bootmem
Global Resource tag name: %s Resource Address: %llx
cvmx_app_id __cvmx_global_resources_init cvmx_create_global_resource cvmx_allocate_global_resource_range free_global_resources %s: Invalid BGX address 0x%llx
%s: Invalid parent node
gpio-leds %s: LEDs not compatible
gpios %s Invalid GPIO in device tree for LED
%s: Invalid GPIO phandle
cavium,octeon-3860-gpio cavium,octeon-7890-gpio %s: Error: Only native OCTEON GPIOs can be used for network LEDs
%s: Could not get GPIO CPU node number
%s: Out of memory!
%s: Error reading the SFP module eeprom for %s
%s(%s, %d, %p): Error: no matching tap for length %d
%s: Invalid GPIO bit(%d)
%s: Unknown GPIO type
%s: Error: missing phy info or cs4343 info for xiface 0x%x, index %d
ERROR: No node expected for interface: %d, port: %d, mode: %s
pip ERROR: pip path not found in device tree ERROR: pip not found in device tree interface@%d ethernet@%x mix%d ERROR: mix%d path not found in device tree
ERROR: %s not found in device tree
%s(0x%x, %d): Unknown phy type, mod_abs changed not registered
cavium,link-status-led %s: Error getting link status LED
%s: Error getting RX activity LED
cavium,rx-activity-blink-rate cavium,rx-timer Error: RX GPIO timer in device tree is out of range! Must be 0..3 cavium,tx-activity-led %s: Error getting TX activity LED
cavium,tx-activity-blink-rate cavium,tx-timer Error: TX GPIO timer in device tree is out of range! Must be 0..3 cavium,error-led cavium,link-poll-interval-ms cavium,activity-poll-interval-ms cavium,rx-activity-led Error: device tree corrupt! cavium,octeon-7890-bgx cavium,octeon-7360-xcv %s: Error: port index (reg) must be 0, not %d.
reg %s: Error: could not get BGX interface address
%s: Device tree BGX node has invalid address 0x%llx
phy-handle %s: Error %d parsing device tree
%s: ERROR: /aliases not found in device tree fdt_addr=%p
%s: ERROR: interface %x pip path not found in device tree
%s: ERROR: interface %x pip not found in device tree
phy cavium,sgmii-mac-phy-mode cavium,force-link-up cavium,sgmii-mac-1000x-mode cavium,disable-autonegotiation cavium,rx-clk-delay-bypass cavium,rx-clk-skew cavium,tx-clk-delay-bypass tx-clk-delay cavium,refclk-sel /aliases No device tree found. Error: No /aliases node in device tree. compatible ERROR: no compatible prop in phy marvell broadcom vitesse vitesse,vsc8490 ethernet-phy-ieee802.3-c22 aquantia cortina cortina,host-mode ti atheros,ar8334 qualcomm,qca8334 atheros,ar8337 qualcomm,qca8337 ethernet-phy-ieee802.3-c45 Unknown PHY compatibility rxaui xaui sgmii qsgmii Unknown PHY host mode ERROR : cannot find phy parent for ipd_port=%d ret=%d
ethernet-phy-nexus cavium,mdio-mux Could not get register value for muxed MDIO bus from DT mdio-parent-bus Invalid SMI offset for muxed MDIO interface in device tree Invalid GPIO for muxed MDIO controller in DT Cannot access parent GPIO node in DT nxp,pca8574 Could not find TWSI address of npx pca8574 GPIO from DT nxp,pca9548 Could not read MUX TWSI address from DT Unknown GPIO type %s
cavium,octeon-3860-mdio ERROR : unable to get reg property in phy mdio ERROR: Could not read phy address from reg in DT Error reading mdio mux information for ipd port %d
Error: missing reg field for bgx port in device tree Error: incompatible Ethernet MAC Nexus in device tree! Device tree BGX node has invalid address 0x%llx
%s: Out of memory
%s: Error parsing phy info for ipd port %d
qsfp-slot sfp-slot cavium,octeon-7890-bgx-port Error: could not parse BGX device tree Error: could not parse Microsemi VSC7224 in DT ERROR: %d:%d:no compatible prop in phy
Error: %d:%d:could not get PHY address
Could not get MDIO base address from reg field %s: Invalid SMI bus address 0x%llx
Invalid MDIO address 0x%llx, could not detect bus and node
%s: Error: incompatible MDIO bus %s for IPD port %d
cortina,cs4343-slice %s: Error parsing cs4343 phy in device tree
%s: Error registering mod_abs changed handler for 0x%x:%d
cortina,cs4343 %s: Unknown board type %d
ERROR: ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found. ERROR: The board type is mis-configured, and software malfunctions are likely. ERROR: All boards require a unique board type to identify them. unknown /soc/uctl /soc/usbn refclk-type refclk-frequency crystal Warning: invalid crystal speed for USB clock type in FDT external Warning: invalid USB clock speed of %u hz in FDT
Warning: invalid USB reference clock type "%s" in FDT
inphi,cs4343 cortina,cs4223 inphi,cs4223 inphi,cs4343-slice cortina,cs4223-slice inphi,cs4223-slice Y Y Z ZH Y Y Y Y h H cvmx_sfp_vsc7224_mod_abs_changed cvmx_sfp_cs4343_mod_abs_changed cvmx_helper_phy_register_mod_abs_changed __cvmx_helper_78xx_parse_phy 0 0 __cvmx_mdio_addr_to_node_bus __cvmx_helper_parse_gpio_leds __alloc_leds __get_led_gpio cvmx_gpio_set_freq __cvmx_helper_parse_bgx_dt __cvmx_bgx_reg_addr_to_xiface __cvmx_helper_parse_bgx_rgmii_dt __cvmx_helper_board_get_port_from_dt
d' __set_gpio __cvmx_gpio_cfg cvmx_helper_board_get_mii_address cvmx_gpio_cfg_sel __cvmx_helper_board_link_get_from_dt SGMII%d: Port %d link timeout
Waiting for link training ERROR: %d:BGX%d:%d: BASE-R PCS block lock lost, need to retry
XAUI/XLAUI/XFI%d: Port %d link timeout
SGMII%d:%d: Timeout waiting for port %d to be idle
BGX%d:%d: SPU stuck in reset
ERROR: %s: SGMII: Timeout waiting for port %u:%d/%d to stop
ERROR: %s: XAUI: Timeout waiting for port %u:%d/%d to stop
P P P P L @ P @ @ @ @cvmx_helper_bgx_shutdown_port ERROR: %s: Failed to initalize pko queues range
WARNING: %s port=%d already %d queues
ERROR: %s port=%d > %d
ERROR: %sL Failed to allocate queue for port=%d count=%d
ERROR: %s port=%d > %d port=%d que_base=%d que_num=%d
cvmx_helper_cfg_show_cfg: interface%d mode %10s nports%4d
pknd[%i][%d]%d pko_port_base[%i][%d]%d pko_port_num[%i][%d]%d
cvmx_helper_cfg_show_cfg: pko_port%d qbase%d nqueues%d interface%d index%d
cvmx_helper_cfg_assert (%s) at %s:%d
pko_port_base != CVMX_HELPER_CFG_INVALID_VALUE /opt/3.1.2j/OCTEON-SDK-3.1.2-p12-L3-603/executive/cvmx-helper-cfg.c pko_port_max >= pko_port_base pko_eid <= 0x14 failed to import config ERROR: %s: failed to allocate internal ports forinterface=%d port=%d cnt=%d
ERROR: %s: failed to allocate queues for port=%d cnt=%d
pko_port_base <= CVMX_HELPER_CFG_MAX_PKO_PORT ERROR: %s: failed to alloc %d queues for pko port=%d
pknd <= CVMX_HELPER_CFG_MAX_PIP_PKND bpid <= CVMX_HELPER_CFG_MAX_PIP_BPID cvm_pko_alloc_iport_and_queues failed. U X X U U W0 W0 U U U V V W0 W0 Ucvmx_pko_queue_grp_alloc cvmx_pko_queue_alloc init_cvmx_pko_que_range cvmx_pko_queue_free cvmx_pko_alloc_iport_and_queues cvmx_helper_cfg_init_pko_iports_and_queues_using_static_config FPA pool status: pools count: %u
---------------------------------------------------- %5s %5s %12s %16s
POOL Size Free Name * %5u %5u %12u %16s %1s
FPA3 on node %u: intr=%#x
%6s %5s %14s %14s %16s %s
Intr AURA Allocated Remaining PKI_POOL WQE_POOL PKO_POOL TIM_POOL DFA_POOL cvmx_fpa3_num_pools cvmx_fpa3_num_auras ERROR: Allocating pcam entry node=%d bank=%d
ERROR: %s is not supported on this chip)
PKI POOL DFLT PKI DFLT AURA ERROR: config cluster group %d ERROR: %s: Failed to allocate pool %d
ERROR: %sL Failed to allocate aura %d
ERROR: pki parse en group %d ERROR: unrecognized qpg_qos = %d INFO:setup_qpg_table: offset %d already reserved
ERROR:setup_qpg_table: no more entries available ERROR: aura %d is > supported in hw
pki-helper:qos-rsrc: ERROR: sso grp not available ERROR: %s POOL %d init failed
ERROR: %s AURA %d init failed
ERROR: %s: sso grp not available
ERROR: %s: POOL %d init failed
ERROR: %s: AURA %d init failed
pki-helper: INFO: qpg entries will be shared pki-helper: ERROR: qpg entries not available pki-helper:gbl: ERROR: sso grp not available ERROR: %s: POOL %u:%d unavailable
ERROR: %s: AURA %u:%d unavailable
pki-helper:port%d:ERROR: qpg entries not available
%s INFO: style will be shared
%s ERROR: style not available
ERROR:pki-helper:intf-init:intf0x%x: global scheduling is in use but is NULL
No pool has setup for intf 0x%x
interface %d on node %d is using global pool
passthrough: INFO: style will be shared passthrough: ERROR: style not available Showing stats for intf 0x%x port %d------------------
END STAUS------------------------
ORDERED Wqe entry for packet %lld
WORD%02d: %016llx aura=0x%x apad=%d chan=0x%x bufs=%d style=0x%x pknd=0x%x len=%d grp=0x%x NULL_NULL ATOMIC tt=%s tag=0x%08x [LAE] lbty=%d%s lcty=%d%s ldty=%d%s lety=%d%s lfty=%d%s lgty=%d%s PF1 PF2 PF3 PF4 vlan valid vlan stacked stat_inc L3 Fragment L3 Broadcast L3 Multicast L2 Broadcast L2 Multicast RAW errlev=%d opcode=0x%x size=%d addr=0x%llx laptr=%d lbptr=%d lcptr=%d ldptr=%d leptr=%d lfptr=%d lgptr=%d vlptr=%d WORD%02d: %016llx
ERROR: Failed to allocate interim style ERROR: %s: new style not available
ERROR: %s: new qpg entry not available
(ENET) (VLAN) (SNAP_PAYLD) (ARP) (RARP) (IP4) (IP4_OPT) (IP6) (IP6_OPT) (IPSEC_ESP) (IPFRAG) (IPCOMP) (TCP) (UDP) (SCTP) (UDP_VXLAN) (GRE) (NVGRE) (GTP) cvmx_sso_set_group_priority cvmx_sso_set_group_core_affinity __cvmx_helper_pki_setup_fpa_pools cvmx_fpa3_num_auras __cvmx_helper_pki_qos_rsrcs __cvmx_helper_pki_port_rsrcs __cvmx_helper_pki_intf_rsrcs cvmx_helper_pki_set_gbl_schd cvmx_helper_pki_init_port
H
P
X
h
p
x
cvmx_helper_pki_route_prt_dmac PKO Cmd-bufs %s: ERROR: in PKO buffer pool
cvmx_helper_pko_pool_init %s(%s): Error: i2c bus undefined for eeprom
%s: Error selecting SFP/QSFP slot
Error: SFP EEPROM checksum information is incorrect Error: Unknown SFP extended identifier 0x%x
Module is not SFP/SFP+/SFP28/QSFP+ %s: Unknown SFP transceiver type 0x%x
%s: Error: mod_abs not set for %s
ethernet,sfp-slot tx_disable mod_abs tx_error rx_los eeprom diag %s(%s): Error: could not get i2c bus from device tree
ethernet,qsfp-slot lp_mode mod_prs select reset interrupt %s: Error parsing QSFP or SFP slots in device tree
cvmx_sfp_read_i2c_eeprom cvmx_sfp_check_mod_abs cvmx_sfp_parse_device_tree cvmx_sfp_parse_sfp cvmx_sfp_parse_qsfp SGMII%x: Port %d link timeout
SGMII%d: Timeout waiting for port %d to be idle
Cavium Inc. OCTEON SDK version 3.1.2-p12, build 603 UNKNOWN WORD0 = %lx
WORD1 = %lx
WORD2 = %lx
Packet Length: %u
Input Port: %u
QoS: %u
Buffers: %u
Buffer Start:%llx
Buffer I : %u
Buffer Back: %u
Buffer Pool: %u
Buffer Data: %llx
Buffer Size: %u
%02x
__cvmx_helper_setup_gmx: Illegal num_ports ERROR: %s: interface %u:%u bad mode
ERROR: %s: Illegal IPD port number %#x
port %d: the number of packets - ipd: %d
port %d: the number of packets - pko: %d
%08x: %0*x DISABLED RGMII GMII SPI PCIE XAUI SGMII PICMG NPI LOOP SRIO ILK RXAUI QSGMII AGL XLAUI XFI 10G_KR 40G_KR4 MIXED
(
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8
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@ @ @ cvmx_helper_get_ipd_port cvmx_helper_get_interface_index_num __int_%d_link_info iface %d failed to alloc link info
Node %d Interface %d has %d ports (%s)
%s: Purged %d packets from SSO
WARNING: %s: Failed to drain some PKO queues
Aligning CN38XX pass 2 IPD counters ERROR: Unable to align IPD counters (PKO failed) ERROR: Unable to align IPD counters (Packet pool empty) ERROR: Unable to align IPD counters GMX RX path timeout waiting for idle GMX TX path timeout waiting for idle AGL RX path timeout waiting for idle AGL TX path timeout waiting for idle IPD reset timeout waiting for idle ERROR: %s failed size %u
x X X L x X X X x h h 8 И Р ( Ҙ ݐ 8 C L M R8 V ^( ^( ^0 [ [ cvmx_helper_shutdown_packet_io_global_cn78xx cvmx_helper_shutdown_packet_io_global cvmx_helper_mem_alloc ERROR: invalid interface=%d in cvmx_ilk_use_la_mode
ERROR: invalid interface=%d in cvmx_ilk_la_mode_enable_rx_calendar
ILK%d:%d: %s: lane assignment conflict
ILK%d: %s: incorrect lane mask: 0x%x
ILK%d: %s: qlm unavailable
clkf_byp cfg_rst_n_clr cfg_tx_idle_set ERROR: Invalid interface %d
ILK%d Channel%d Rx: %d packets %d bytes
ILK%d Channel%d Tx: %d packets %d bytes
cvmx_ilk_start_interface setup_red: cvmx_helper_get_bpid(%d, %d) = %d
Warning: Enabling IPD when IPD already enabled. L2C counters don't support clear on read for this chip
ERROR: cvmx_l2c_get_tag association out of range ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)
ERROR: Cannot use %s on OCTEON CN68XX, use cvmx_l2c_get_tag_v2 instead!
ERROR: cvmx_l2c_get_tag_v2: TAD#%d out of range
ERROR: cvmx_l2c_lock_line: addr 0x%llx in LMC hole.
ERROR: cvmx_l2c_flush_line index out of range. ERROR: cvmx_l2c_flush_line association out of range. WARNING: Invalid memory size(%lld) requested, should be <= %lld
ERROR: Invalid DRAM size (%lld) requested, refer to L2C_BIG_CTL[maxdram] for valid options.
WARNING: Changing number of Virtual Machine IDs is not allowed after Virtualization is enabled WARNING: cvmx_l2c_vrt_set_max_virtids: Invalid number of Virtual Machine IDs(%d) requested, max allowed %d
WARNING: cvmx_l2c_vrt_get_max_virtids: Invalid number of Virtual IDs initialized (%d)
WARNING: cvmx_l2c_vrt_set_memsz: Changing the size of the memory after Virtualization is enabled is not allowed. WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), greater than available on the chip
WARNING: Invalid virtual memory size(%d) requested, should be <= %d
WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), refer to L2C_VRT_CTL[MEMSZ] for more information
WARNING: cvmx_l2c_vrt_assign_virt_id: Max %d number of virtids are allowed, passed %d.
WARNING: cvmx_l2c_vrt_assign_virt_id: Changing virtid of core #%d to %d from %d.
WARNING: cvmx_l2c_vrt_assign_virt_id: Invalid coremask(0x%x) passed
WARNING: cvmx_l2c_vrt_memprotect: Virtualization is not enabled. WARNING: cvmx_l2c_vrt_memprotect: Virtualization id is greater than max allowed WARNING: cvmx_l2c_vrt_memprotect: Start address is not aligned WARNING: cvmx_l2c_vrt_memprotect: Invalid start address(0x%llx), size(%d), cannot protect memory in hole.
WARNING: cvmx_l2c_vrt_memprotect: Virtualization id (%d) is not assigned to any core.
cvmx_l2c_get_tag 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10 22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19 22 21 13 11 01 02 07 19 03 18 10 12 20 06 04 08 17 05 14 16 00 09 15 22 21 11 13 04 08 17 05 14 16 00 09 15 06 01 02 07 19 03 18 10 12 20 22 21 02 19 18 17 16 09 14 13 20 11 10 01 08 03 06 15 04 07 05 12 00 22 21 19 02 08 03 06 15 04 07 05 12 00 01 18 17 16 09 14 13 20 11 10 No default LLM configuration available for board %s (%d)
Skipping llm configuration for simulator. Warning: preliminary DFA memory configuration Using default LLM configuration for board %s (%d)
Configuring %d llm port(s).
Error creating rldram configuration Warning: Enabling PKI when PKI already enabled. PKI_SFT_RST is not active PKI_SFT_RST is busy ERROR: Configuring PKIND pkind = %d cluster_group = %d style = %d
ERROR: qpg offset %d is >= 2048
ERROR: Invalid pcam entry %d
ERROR: %s aura = %d
ERROR: aura=%d or bpid=%d is out or range
ERROR: %s channel = %d bpid = %d
%d PADD %-16lu GRP_OK %-16lu GRP_BAD %-16lu LAURA %-16lu
--------------Cluster %1d Bank %1d-------------
index TERM DATA, ACTION
%d %-16lx
--------------Cluster %1d Bank %1d---------------------
%-10s%-17s%-19s%-18s index TERM1:TERM0 Style1:Style0 Data1:Data0 %-6s ACTION[pmc:style_add:pf:setty:advance]
%-13d %-2x:%x %-2x:%x %-8x:%x %-2x:%-2x :%-1x :%2x :%-2x ERROR: PKIND %d is beyond range
Showing stats for pkind %d------------------
cluster group: %d
cluster mask of the group: 0x%x
pkind %d config 0x%llx
initial parse Mode: %d
initial_style: %d
style_alg: 0x%llx
style_cfg: 0x%llx
style_cfg2: 0x%llx
style_buf: 0x%llx
qpg base: %d
qpg qos: %d
qpg index %d: 0x%llx
count stuck for 0x%llx
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ERROR: Failed to allocate style, none available ERROR Failed to release style %d
ERROR: Invalid node number %d
ERROR: Failed to create Cluster group global resource INFO: cl_grp %d is already reserved
Warning: Failed to alloc cluster grp ERROR Failed to release cluster group %d
ERROR: Failed to create Clusters global resource ERROR: allocating cluster %d
ERROR: allocating clusters ERROR: freeing cluster %d
ERROR: Failed to create pki pcam global resource ERROR: PCAM :index %d not available in cluster %d bank %d ERROR: Failed to create qpg_entry global resource INFO: qpg entry %d is already reserved
ERROR: Failed to allocate qpg entry ERROR Failed to release qpg offset %d ERROR pki-rsrc: Failed to release all styles ERROR pki-rsrc:Failed to release all styles ERROR pki-rsrc:Failed to release all qpg entries ERROR pki-rsrc:Failed to release all bpids ERROR pki-rsrc:Failed to release all pcan entries ERROR: Failed to create bpid global resource INFO: bpid %d is already reserved
ERROR: Failed to allocate bpid ERROR Failed to release bpid %d
ERROR: Failed to create MTAG-IDX global resource INFO: MTAG index %d is already reserved
ERROR: Failed to allocate MTAG index ERROR Failed to release MTAG index %d
cvmx_fpa3_num_auras pko_port %d (interface%d index%d) has %d queues (queue base = %d)
interface < CVMX_HELPER_MAX_IFACE /opt/3.1.2j/OCTEON-SDK-3.1.2-p12-L3-603/executive/cvmx-pko.c index >= 0 index < 4 index == 0 index < 256 index < 32 index < 8 Warning: Enabling PKO when PKO already enabled. ERROR: %s: Static priority queues aren't contiguous or don't start at base queue. q: %d, eq: %d
ERROR: %s: Static priority queues don't start at base queue. sq: %d
ERROR: %s: Invalid priority %llu
ERROR: %s: Unable to allocate output buffer
ERROR: %s: Port already setup
ERROR: %s: Command queue initialization failed. pko_port%d base_queue%d num_queues%d queue%d.
Warning: Invalid port_base X @ ǔ ` T Έ x h X H 8 ( ̸ ̸cvmx_pko2_config_port ERROR : Failed to initalize pko internal port range interface=%d port=%d port_base=%d port_cnt=%d
ERROR: %s: queue level %#x invalid
allocate reserve ERROR: Failed to create PKO3 resource: %lx-%lx
ERROR: Failed to %s PKO3 tag %lx:%lx, %i %i %i %i.
cvmx_pko3_dq_globl_param_0 cvmx_pko3_num_level_queues __cvmx_pko_get_queues_resource_tag cvmx_pko3_global_dq_table ERROR: %s: xiface %#x has no IPD port
%s: ERROR: IPD %#x already registered
WARNING: %s:ipd=%#x already released
%s: ERROR: channel %#x not recognized
ERROR: %s: model or level %#x invalid
__cvmx_pko3_ipd_dq_register __cvmx_pko3_ipd_dq_unregister cvmx_pko3_map_channel cvmx_pko3_sq_config_children
WARNING: Entry %d already on list %s, but we tried to add it to %s
head=%llu(0x%llx) tail=%llu(0x%llx) One element Multiple elements Empty WARNING: %s: SSO already down
head_ptr.s.ptr != tail_ptr.s.ptr, idx: %d
WARNING: %s: SSO already enabled
ERROR: %s: Out of memory
cvmx_pow_capture: Buffer too small. At least %d bytes are needed.
cvmx_pow_dump: Buffer too small Core %d State: tag=%s,0x%08x grp=%d wqp=0x%016llx index=%d head prev=%d tail next=%d pend_switch=%d pend_switch_full=%d pend_switch_null=%d pend_desched=%d pend_desched_switch=%d pend_nosched=%d pend_grp=%d (Waiting for work) (Getting work) pend_null_rd=%d pend_nosched_clr=%d pend_index=%d pending tag=%s,0x%08x pend_wqp=0x%016llx
Queue %da Memory (is head) Queue %da Memory Queue %db Memory (is head) Queue %db Memory Entry %d(%-10s): tag=%s,0x%08x grp=%d wqp=0x%016llx nosched=%d cvmx_pow_dump: Buffer too small, pow_dump_t = 0x%x, buffer_size = 0x%x
Free List: qnum_head=%d, qnum_tail=%d
Free0: valid=%d, one=%d, head=%llu, tail=%llu
Free1: valid=%d, one=%d, head=%llu, tail=%llu
Free2: valid=%d, one=%d, head=%llu, tail=%llu
Core %d State: tag=%s,0x%08x pend_alloc_we=%d next_index=%d fwd_index=%d sso_core_state %lx
cvmx_pow_display: Buffer too small. At least %d bytes are needed.
POW Display Start POW Display End Unknown Free List Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Core 0 Core 1 Core 2 Core 3 Core 4 Core 5 Core 6 Core 7 Core 8 Core 9 Core 10 Core 11 Core 12 Core 13 Core 14 Core 15 Core 16 Core 17 Core 18 Core 19 Core 20 Core 21 Core 22 Core 23 Core 24 Core 25 Core 26 Core 27 Core 28 Core 29 Core 30 Core 31 Desched 0 Desched 1 Desched 2 Desched 3 Desched 4 Desched 5 Desched 6 Desched 7 Desched 8 Desched 9 Desched 10 Desched 11 Desched 12 Desched 13 Desched 14 Desched 15 Desched 16 Desched 17 Desched 18 Desched 19 Desched 20 Desched 21 Desched 22 Desched 23 Desched 24 Desched 25 Desched 26 Desched 27 Desched 28 Desched 29 Desched 30 Desched 31 Desched 32 Desched 33 Desched 34 Desched 35 Desched 36 Desched 37 Desched 38 Desched 39 Desched 40 Desched 41 Desched 42 Desched 43 Desched 44 Desched 45 Desched 46 Desched 47 Desched 48 Desched 49 Desched 50 Desched 51 Desched 52 Desched 53 Desched 54 Desched 55 Desched 56 Desched 57 Desched 58 Desched 59 Desched 60 Desched 61 Desched 62 Desched 63 Nosched 0
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cfg_cdr_trunc cfg_rst_n_set cfg_tx_idle_clr ir50dac div4_byp serdes_pll_byp spdsel_byp biasdrv_hs_ls_byp biasdrv_hf_byp biasdrv_lf_ls_byp biasdrv_lf_byp tcoeff_hf_byp tcoeff_hf_ls_byp tcoeff_lf_ls_byp tcoeff_lf_byp rx_cap_gen2 rx_eq_gen2 serdes_tx_byp ERROR: cvmx_qlm_init: JTAG chain larger than XOR ref size cvmx_qlm_jtag ERROR: cvmx_qlm_init: Error in creating %s named block
cfg_rxd_set Invalid QLM(%d) passed
%s: Unsupported OCTEON model
%29s Field[:] Lane %d %20s[%3d:%3d] biasdrv_ tcoeff_ %4llu (0x%04llx) d | ` H H j 5 j 5 cvmx_qlm_measure_clock_cn7xxx prbs_err_cnt prbs_lock jtg_prbs_rx_rst_n jtg_prbs_tx_rst_n jtg_prbs_mode jtg_prbs_rst_n jtg_run_prbs31 jtg_run_prbs7 Unused1 cfg_pwrup_set cfg_pwrup_clr cfg_tx_byp cfg_tx_byp_inv cfg_tx_byp_val cfg_loopback shlpbck sl_enable sl_posedge_sample trimen lowf_byp Unused4 interpbw pll_cpb pll_cps pll_diffamp cfg_err_thr cfg_rx_idle_set cfg_rx_idle_clr cfg_rx_idle_thr cfg_com_thr cfg_rx_offset cfg_skp_max cfg_skp_min cfg_fast_pwrup Unused6 detected_n detected_p dbg_res_rx dbg_res_tx cfg_tx_pol_set cfg_tx_pol_clr cfg_rx_pol_set cfg_rx_pol_clr cfg_rxd_clr cfg_rxd_wait cfg_cdr_limit cfg_cdr_rotate cfg_cdr_bw_ctl cfg_cdr_rqoffs cfg_cdr_inc2 cfg_cdr_inc1 fusopt_voter_sync rndt hcya hyst idle_dac bg_ref_sel ic50dac tx_rout_comp_bypass tx_rout_comp_value tx_res_offset rx_rout_comp_bypass rx_rout_comp_value rx_res_offset rx_cap_gen1 rx_eq_gen1 div5_byp cfg_indep_dis Unused2 Unused3 Unused5
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RAIDcmdq ERROR: %s: fpa pool %d configuration failed
ERROR: cvmx_raid_shutdown: RAID not idle. cvmx_raid_initialize ERROR: %s: invalid base or cnt. range_addr=0x%llx, owner=0x%llx, size=%d base+cnt=%d
ERROR: %s: invalid base or cnt size=%d base=%d
ERROR: %s: invalid base or cnt size=%d base+cnt=%d
ERROR: %s: invalid base or cnt size=%d base=%d
index=%d: owner %llx
cvmx_range_reserve __cvmx_range_is_allocated cvmx_range_free_with_base cvmx_range_get_owner ERROR: failed to create sso global resource for node=%d
Warning: SSO groups %i-%i already reserved.
ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than the minimal ticks allowed by hardware %lu(ns)
ERROR: cvmx_tim_setup: Requested tick %lu(ns) is greater than the max ticks %lu(ns)
ERROR: cvmx_tim_setup: num_buckets out of range ERROR: cvmx_tim_setup: allocation problem, size = %luKB
TIMER_NAMED_BLOCK WARNING: cvmx_mbox_register: Illegal mbox %u
__pci_console !Core XX taking focus. T8: T9 S0A !Uknown core. Focus not changed. F !Core is not in the exception handler. Focus not changed. J !Focus core was added to the mask. I + - cvmx-debug-globals Failed allocating debug globals, spinining. Wrong version on the globals struct spinining; expected %d, got: %d.
Unexpected debug-mode exception occured at 0x%llx, 0x%llx spinning
Unknown communication spinning: %lld > %d.
finished. D0 p p p p p p p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 p0 px pp x qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh r qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh qh x qh r qh qh qh qh th z0 qh yP s qh qh u qh qh qh qh qh qh qh qh qh qh qh qh t qh qh qh qh qh qh s qh t qh yp tH x qh s s qh qh v qh qh qh qh qh x qh qh qh qh qh qh w `0123456789ABCDEF 0123456789ABCDEF cvmx_interrupt_map: Illegal irq_number %d
cvmx_interrupt_register: Illegal irq_number 0x%x
%3s ($%02d): 0x%08x%08x %3s ($%02d): 0x%08x%08x
Floating point registers:
f%02d:0x%016llx flt:%-17.9g dbl:%-24.17g
%16s: 0x%08x
FIR FCSR %16s: 0x%08x%08x
Trap Core %d: Unhandled Exception. Cause register decodes to:
%s
Backtrace:
__cvmx_interrupt_ciu2: Received unhandled interrupt sum:%d
__cvmx_interrupt_ciu2: Received unhandled interrupt %d:%d
Unknown CIU2 bit: %d
Dcache error detected: core: %d, way: %d, va 9:7: 0x%x
Icache error detected: core: %d, way : %d, va 9:3 = 0x%x
Cache error exception: core %d
Bus error detected due to DID timeout: core: %d
Bus error detected due to write buffer parity: core: %d
cvmx_error_initialize() failed
clearing pending SLI_INT_SUM[RML_TO] interrupt (ignore)
8 8 x 8 p p p p h 8 8 8 ` X P 8 H @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 0 ( 8 8 8 x x 8 r0 at v0 v1 a0 a1 a2 a3 t0 t1 t2 t3 t4 t5 t6 t7 s0 s1 s2 s3 s4 s5 s6 s7 t8 t9 k0 k1 gp sp s8 ra Interrupt TLB modification tlb load/fetch tlb store address exc, load/fetch address exc, store bus error, instruction fetch bus error, load/store syscall breakpoint reserved instruction cop unusable arithmetic overflow trap floating point exc cop2 exception mdmx unusable watch machine check cache error Obsolete bootloader, can't run application Warning: newer boot descripter version than expected ERROR: Incompatible CVMX descriptor passed by bootloader: %d.%d
ERROR : Corrupt Device Tree. Using device tree ERROR: Using debug and break together in not supported. break= debug= CVMX BIST FAILURE: COP0_CACHE_ERR: 0x%llx
BIST FAILURE: COP0_CVM_MEM_CTL: 0x%llx
< 0 $ | p d X L @ 4 ( t h \ P D 8 , p X @ Àotrace_stub_handler H otc_call_trace otrace_log_enqueue otrace_log_vars %s: this entry should be full
%s: invalid var size%d @ %p (probe index%d var index%d), ignored
function_entry function_exit invalid_probe_type probe addr %p type %s:
var_ltype%d (elem%d) arg1=0x%llx arg2=0x%llx found at %d %d vars not found otc_bufs %s: no otc buffer for core %d
otl_queue%d %s: no otl buf on core %d
cvmx-coredump Core file is ready to dump
%s:Max number of memory range exceeded
%s: Memory range not found
cvmx_coredump_add_mem_range cvmx_coredump_delete_mem ERROR: attempting to initialize DFA when no DFA hardware present
. cvmx-error table full
cvmx-error remove couldn't find requested register
cvmx-error change couldn't find requested register
cvmx-error enable couldn't find requested register
cvmx-error disable couldn't find requested register
All cores except node %d, core %d powered down
Setting node %d, core %d to wait forever
Single-bit L2C ECC error generated artificially on ECC[0]
Single-bit L2C ECC error generated artificially on ECC[1]
Double-bit L2C ECC error generated artifically on ECC[0:1]
Unknown L2 cache error detected
L2D double-bit L2D error: %d
L2D double-bit SBF error: %d
L2D double-bit FBF error: %d
L2D single-bit L2D error: %d
L2D single-bit SBF error: %d
L2D single-bit FBF error: %d
L2 cache %s-bit ECC error detected
single Node: %d, TAD: %d, L2D index: 0x%x, quad half: 0x%x, quad number: 0x%x, error syndrome: 0x%x
double
Cannot continue due to uncorrectable cache line!
Please reset or power cycle this system!
remote Single-bit L2C TAG ECC error generated artificially on ECC[0]
Single-bit TAG L2C ECC error generated artificially on ECC[1]
Double-bit TAG L2C ECC error generated artifically on ECC[0:1]
L2 cache %s-bit %stag ECC error detected
Node: %d, TAD: %d, L2D index: 0x%x, way: 0x%x, error syndrome: 0x%x
ERROR DDR%d ECC: %d Single bit corrections, %d Double bit errors
DDR%d ECC: Failing dimm: %u
DDR%d ECC: Failing rank: %u
DDR%d ECC: Failing bank: %u
DDR%d ECC: Failing row: 0x%x
DDR%d ECC: Failing column: 0x%x
TAD: %d, L2D index: 0x%x, way: 0x%x, error syndrome: 0x%x
Unknown L2 cache error detected
L2D double-bit L2D error: %d
L2D double-bit VBF error: %d
L2D single-bit L2D error: %d
L2D single-bit VBF error: %d
TAD: %d, L2D wayindex: 0x%x, error syndrome: 0x%x
VBF error syndrome: 0x%x
ERROR PBANK_LSB: %d, ROW_LSB: %d, Row bits: %d, Col bits: %d, Row mask: 0x%x, Col mask: 0x%x
ERROR LMC%d ECC: sec_err:%d ded_err:%d
LMC%d ECC: Failing dimm: %u
LMC%d ECC: Failing rank: %u
LMC%d ECC: Failing bank: %u
LMC%d ECC: Failing row: 0x%x
LMC%d ECC: Failing column: 0x%x
LMC%d ECC: syndrome: 0x%x
Failing Address: 0x%016llx, Data: 0x%016llx
ERROR DFA_ERR[CP2DBE]: DFA PP-CP2 Double Bit Error Detected
ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected
ERROR DFA_ERR[CP2SBE]: DFA PP-CP2 Single Bit Error Corrected
ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected
ERROR DFA_ERR[DTEDBE]: DFA DTE 29b Double Bit Error Detected
ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected
ERROR DFA_ERR[DTESBE]: DFA DTE 29b Single Bit Error Corrected
ERROR L2D_ERR[DED_ERR] ECC double: fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx
ERROR L2D_ERR[SEC_ERR] ECC single: fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx
ERROR L2T_ERR[DED_ERR]: double bit: fadr: 0x%x, fset: 0x%x, fsyn: 0x%x
ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n could not find an available/unlocked set (for replacement).
ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of the INDEX (which is ignored by HW - but reported to SW).
ERROR L2T_ERR[SEC_ERR]: single bit: fadr: 0x%x, fset: 0x%x, fsyn: 0x%x
ERROR POW_ECC_ERR[DBE]: POW double bit error
ERROR POW_ECC_ERR[IOP0]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state
ERROR POW_ECC_ERR[IOP1]: Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state
ERROR POW_ECC_ERR[IOP2]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC
ERROR POW_ECC_ERR[IOP3]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL
ERROR POW_ECC_ERR[IOP4]: Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL
ERROR POW_ECC_ERR[IOP5]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending
ERROR POW_ECC_ERR[IOP6]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending
ERROR POW_ECC_ERR[IOP7]: Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending
ERROR POW_ECC_ERR[IOP8]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending
ERROR POW_ECC_ERR[IOP9]: Received illegal opcode
ERROR POW_ECC_ERR[IOP10]: Received ADD_WORK with tag specified as NULL_NULL
ERROR POW_ECC_ERR[IOP11]: Received DBG load from PP with DBG load pending
ERROR POW_ECC_ERR[IOP12]: Received CSR load from PP with CSR load pending
ERROR POW_ECC_ERR[RPE]: Remote pointer error
ERROR POW_ECC_ERR[SBE]: POW single bit error
ERROR GMXX_RXX_INT_REG(0,4)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,4)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(0,4)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,4)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,4)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,4)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,4)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,4)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,4)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,4)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,4)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(0,4)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(1,4)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,4)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(1,4)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,4)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,4)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,4)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,4)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,4)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,4)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,4)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,4)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(1,4)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(2,4)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,4)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(2,4)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,4)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,4)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,4)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,4)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,4)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,4)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,4)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,4)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(2,4)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(3,4)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,4)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(3,4)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,4)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,4)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,4)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,4)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,4)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,4)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,4)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,4)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(3,4)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_TX_INT_REG(4)[PKO_NXA]: Port address out-of-range from PKO Interface
ERROR GMXX_TX_INT_REG(4)[UNDFLW]: TX Underflow
ERROR GMXX_TX_INT_REG(4)[PTP_LOST]: A packet with a PTP request was not able to be
sent due to XSCOL
ERROR PCSX_INTX_REG(0,4)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(0,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(0,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(0,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(0,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,4)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(1,4)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(1,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(1,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(1,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(1,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,4)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(2,4)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(2,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(2,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(2,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(2,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,4)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(3,4)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(3,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(3,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(3,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(3,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,4)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSXX_INT_REG(4)[TXFLT]: None defined at this time, always 0x0
ERROR PCSXX_INT_REG(4)[RXBAD]: Set when RX state machine in bad state
ERROR PCSXX_INT_REG(4)[RXSYNBAD]: Set when RX code grp sync st machine in bad state
in one of the 4 xaui lanes
ERROR PCSXX_INT_REG(4)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes
ERROR PCSXX_INT_REG(4)[SYNLOS]: Set when Code group sync lost on 1 or more lanes
ERROR PCSXX_INT_REG(4)[ALGNLOS]: Set when XAUI lanes lose alignment
ERROR PCSXX_INT_REG(4)[DBG_SYNC]: Code Group sync failure debug help, see Note below
ERROR GMXX_RXX_INT_REG(0,3)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,3)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(0,3)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,3)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,3)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,3)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,3)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,3)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,3)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,3)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,3)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(0,3)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(1,3)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,3)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(1,3)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,3)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,3)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,3)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,3)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,3)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,3)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,3)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,3)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(1,3)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(2,3)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,3)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(2,3)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,3)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,3)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,3)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,3)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,3)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,3)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,3)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,3)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(2,3)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(3,3)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,3)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(3,3)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,3)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,3)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,3)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,3)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,3)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,3)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,3)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,3)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(3,3)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_TX_INT_REG(3)[PKO_NXA]: Port address out-of-range from PKO Interface
ERROR GMXX_TX_INT_REG(3)[UNDFLW]: TX Underflow
ERROR GMXX_TX_INT_REG(3)[PTP_LOST]: A packet with a PTP request was not able to be
sent due to XSCOL
ERROR PCSX_INTX_REG(0,3)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(0,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(0,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(0,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(0,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,3)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(1,3)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(1,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(1,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(1,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(1,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,3)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(2,3)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(2,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(2,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(2,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(2,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,3)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(3,3)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(3,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(3,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(3,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(3,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,3)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSXX_INT_REG(3)[TXFLT]: None defined at this time, always 0x0
ERROR PCSXX_INT_REG(3)[RXBAD]: Set when RX state machine in bad state
ERROR PCSXX_INT_REG(3)[RXSYNBAD]: Set when RX code grp sync st machine in bad state
in one of the 4 xaui lanes
ERROR PCSXX_INT_REG(3)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes
ERROR PCSXX_INT_REG(3)[SYNLOS]: Set when Code group sync lost on 1 or more lanes
ERROR PCSXX_INT_REG(3)[ALGNLOS]: Set when XAUI lanes lose alignment
ERROR PCSXX_INT_REG(3)[DBG_SYNC]: Code Group sync failure debug help, see Note below
ERROR GMXX_RXX_INT_REG(0,2)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,2)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(0,2)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,2)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,2)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,2)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,2)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,2)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,2)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,2)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,2)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(0,2)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(1,2)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,2)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(1,2)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,2)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,2)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,2)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,2)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,2)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,2)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,2)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,2)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(1,2)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(2,2)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,2)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(2,2)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,2)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,2)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,2)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,2)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,2)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,2)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,2)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,2)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(2,2)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(3,2)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,2)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(3,2)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,2)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,2)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,2)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,2)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,2)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,2)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,2)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,2)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(3,2)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_TX_INT_REG(2)[PKO_NXA]: Port address out-of-range from PKO Interface
ERROR GMXX_TX_INT_REG(2)[UNDFLW]: TX Underflow
ERROR GMXX_TX_INT_REG(2)[PTP_LOST]: A packet with a PTP request was not able to be
sent due to XSCOL
ERROR PCSX_INTX_REG(0,2)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(0,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(0,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(0,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(0,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,2)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(1,2)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(1,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(1,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(1,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(1,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,2)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(2,2)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(2,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(2,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(2,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(2,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,2)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(3,2)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(3,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(3,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(3,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(3,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,2)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSXX_INT_REG(2)[TXFLT]: None defined at this time, always 0x0
ERROR PCSXX_INT_REG(2)[RXBAD]: Set when RX state machine in bad state
ERROR PCSXX_INT_REG(2)[RXSYNBAD]: Set when RX code grp sync st machine in bad state
in one of the 4 xaui lanes
ERROR PCSXX_INT_REG(2)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes
ERROR PCSXX_INT_REG(2)[SYNLOS]: Set when Code group sync lost on 1 or more lanes
ERROR PCSXX_INT_REG(2)[ALGNLOS]: Set when XAUI lanes lose alignment
ERROR PCSXX_INT_REG(2)[DBG_SYNC]: Code Group sync failure debug help, see Note below
ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface
ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow
ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be
sent due to XSCOL
ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0
ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state
ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state
in one of the 4 xaui lanes
ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes
ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes
ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment
ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below
ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error
ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
(SGMII/1000Base-X only)
ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other
than /T/. The error propagation control
character /E/ will be included as part of the
frame and does not cause a frame termination.
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data
(XAUI/RXAUI Mode only)
ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below
1) MSG_TYPE field not 6'b00_0000
i.e. it is not a FLOW CONTROL message, which
is the only defined type for HiGig2
2) FWD_TYPE field not 2'b00 i.e. Link Level msg
which is the only defined type for HiGig2
3) FC_OBJECT field is neither 4'b0000 for
Physical Link nor 4'b0010 for Logical Link.
Those are the only two defined types in HiGig2
ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
a Control Character is found in the message
bytes after the K.SOM
NOTE: HG2CC has higher priority than HG2FLD
i.e. a HiGig2 message that results in HG2CC
getting set, will never set HG2FLD.
ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface
ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow
ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be
sent due to XSCOL
ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed
ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow
condition
ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow
condition
ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock
failure occurs
Cannot fire in loopback1 mode
ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad
state. Should never be set during normal operation
ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help
ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0
ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state
ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state
in one of the 4 xaui lanes
ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes
ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes
ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment
ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below
ERROR ILK_GBL_INT[RXF_LNK0_PERR]: RXF parity error occurred on RxLink0 packet data. Packet will
be marked with error at eop
ERROR ILK_GBL_INT[RXF_LNK1_PERR]: RXF parity error occurred on RxLink1 packet data
Packet will be marked with error at eop
ERROR ILK_GBL_INT[RXF_CTL_PERR]: RXF parity error occurred on sideband control signals. Data
cycle will be dropped.
ERROR ILK_GBL_INT[RXF_POP_EMPTY]: RXF underflow
ERROR ILK_GBL_INT[RXF_PUSH_FULL]: RXF overflow
ERROR ILK_TXX_INT(0)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles
followed by EOP. PKO config assigned multiple engines to the
same ILK Tx Link.
ERROR ILK_TXX_INT(0)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by
ILK_TXX_PIPE
ERROR ILK_TXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow
ERROR ILK_TXX_INT(1)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles
followed by EOP. PKO config assigned multiple engines to the
same ILK Tx Link.
ERROR ILK_TXX_INT(1)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by
ILK_TXX_PIPE
ERROR ILK_TXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow
ERROR ILK_RXX_INT(0)[CRC24_ERR]: Burst CRC24 error. All open packets will be receive an error.
ERROR ILK_RXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow
ERROR ILK_RXX_INT(0)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown
control word type.
ERROR ILK_RXX_INT(0)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX
ERROR ILK_RXX_INT(0)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or
because ILK_RXX_CFG1[PKT_ENA]=0
ERROR ILK_RXX_INT(0)[PKT_DROP_SOP]: Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,
lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0 | $RW
because ILK_RXX_CFG1[PKT_ENA]=0
***NOTE: Added in pass 2.0
ERROR ILK_RXX_INT(1)[CRC24_ERR]: Burst CRC24 error. All open packets will be receive an error.
ERROR ILK_RXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow
ERROR ILK_RXX_INT(1)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown
control word type.
ERROR ILK_RXX_INT(1)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX
ERROR ILK_RXX_INT(1)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or
because ILK_RXX_CFG1[PKT_ENA]=0
ERROR ILK_RXX_INT(1)[PKT_DROP_SOP]: Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,
lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0 | $RW
because ILK_RXX_CFG1[PKT_ENA]=0
***NOTE: Added in pass 2.0
ERROR ILK_RX_LNEX_INT(0)[SERDES_LOCK_LOSS]: Rx SERDES loses lock
ERROR ILK_RX_LNEX_INT(0)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will
automatically attempt to regain word boundary sync
ERROR ILK_RX_LNEX_INT(0)[CRC32_ERR]: Diagnostic CRC32 errors
ERROR ILK_RX_LNEX_INT(0)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of
(SYNC,SCRAM,SKIP,DIAG)
ERROR ILK_RX_LNEX_INT(0)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state
mismatches
ERROR ILK_RX_LNEX_INT(0)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.
ERROR ILK_RX_LNEX_INT(0)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'
(healthy) to a '0' (problem)
ERROR ILK_RX_LNEX_INT(0)[STAT_CNT_OVFL]: Rx lane statistic counter overflow
ERROR ILK_RX_LNEX_INT(0)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches
the burst control unit (as deonted by
ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
packets will receive an error.
ERROR ILK_RX_LNEX_INT(1)[SERDES_LOCK_LOSS]: Rx SERDES loses lock
ERROR ILK_RX_LNEX_INT(1)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will
automatically attempt to regain word boundary sync
ERROR ILK_RX_LNEX_INT(1)[CRC32_ERR]: Diagnostic CRC32 errors
ERROR ILK_RX_LNEX_INT(1)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of
(SYNC,SCRAM,SKIP,DIAG)
ERROR ILK_RX_LNEX_INT(1)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state
mismatches
ERROR ILK_RX_LNEX_INT(1)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.
ERROR ILK_RX_LNEX_INT(1)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'
(healthy) to a '0' (problem)
ERROR ILK_RX_LNEX_INT(1)[STAT_CNT_OVFL]: Rx lane statistic counter overflow
ERROR ILK_RX_LNEX_INT(1)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches
the burst control unit (as deonted by
ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
packets will receive an error.
ERROR ILK_RX_LNEX_INT(2)[SERDES_LOCK_LOSS]: Rx SERDES loses lock
ERROR ILK_RX_LNEX_INT(2)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will
automatically attempt to regain word boundary sync
ERROR ILK_RX_LNEX_INT(2)[CRC32_ERR]: Diagnostic CRC32 errors
ERROR ILK_RX_LNEX_INT(2)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of
(SYNC,SCRAM,SKIP,DIAG)
ERROR ILK_RX_LNEX_INT(2)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state
mismatches
ERROR ILK_RX_LNEX_INT(2)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.
ERROR ILK_RX_LNEX_INT(2)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'
(healthy) to a '0' (problem)
ERROR ILK_RX_LNEX_INT(2)[STAT_CNT_OVFL]: Rx lane statistic counter overflow
ERROR ILK_RX_LNEX_INT(2)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches
the burst control unit (as deonted by
ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
packets will receive an error.
ERROR ILK_RX_LNEX_INT(3)[SERDES_LOCK_LOSS]: Rx SERDES loses lock
ERROR ILK_RX_LNEX_INT(3)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will
automatically attempt to regain word boundary sync
ERROR ILK_RX_LNEX_INT(3)[CRC32_ERR]: Diagnostic CRC32 errors
ERROR ILK_RX_LNEX_INT(3)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of
(SYNC,SCRAM,SKIP,DIAG)
ERROR ILK_RX_LNEX_INT(3)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state
mismatches
ERROR ILK_RX_LNEX_INT(3)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.
ERROR ILK_RX_LNEX_INT(3)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'
(healthy) to a '0' (problem)
ERROR ILK_RX_LNEX_INT(3)[STAT_CNT_OVFL]: Rx lane statistic counter overflow
ERROR ILK_RX_LNEX_INT(3)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches
the burst control unit (as deonted by
ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
packets will receive an error.
ERROR ILK_RX_LNEX_INT(4)[SERDES_LOCK_LOSS]: Rx SERDES loses lock
ERROR ILK_RX_LNEX_INT(4)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will
automatically attempt to regain word boundary sync
ERROR ILK_RX_LNEX_INT(4)[CRC32_ERR]: Diagnostic CRC32 errors
ERROR ILK_RX_LNEX_INT(4)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of
(SYNC,SCRAM,SKIP,DIAG)
ERROR ILK_RX_LNEX_INT(4)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state
mismatches
ERROR ILK_RX_LNEX_INT(4)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.
ERROR ILK_RX_LNEX_INT(4)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'
(healthy) to a '0' (problem)
ERROR ILK_RX_LNEX_INT(4)[STAT_CNT_OVFL]: Rx lane statistic counter overflow
ERROR ILK_RX_LNEX_INT(4)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches
the burst control unit (as deonted by
ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
packets will receive an error.
ERROR ILK_RX_LNEX_INT(5)[SERDES_LOCK_LOSS]: Rx SERDES loses lock
ERROR ILK_RX_LNEX_INT(5)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will
automatically attempt to regain word boundary sync
ERROR ILK_RX_LNEX_INT(5)[CRC32_ERR]: Diagnostic CRC32 errors
ERROR ILK_RX_LNEX_INT(5)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of
(SYNC,SCRAM,SKIP,DIAG)
ERROR ILK_RX_LNEX_INT(5)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state
mismatches
ERROR ILK_RX_LNEX_INT(5)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.
ERROR ILK_RX_LNEX_INT(5)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'
(healthy) to a '0' (problem)
ERROR ILK_RX_LNEX_INT(5)[STAT_CNT_OVFL]: Rx lane statistic counter overflow
ERROR ILK_RX_LNEX_INT(5)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches
the burst control unit (as deonted by
ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
packets will receive an error.
ERROR ILK_RX_LNEX_INT(6)[SERDES_LOCK_LOSS]: Rx SERDES loses lock
ERROR ILK_RX_LNEX_INT(6)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will
automatically attempt to regain word boundary sync
ERROR ILK_RX_LNEX_INT(6)[CRC32_ERR]: Diagnostic CRC32 errors
ERROR ILK_RX_LNEX_INT(6)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of
(SYNC,SCRAM,SKIP,DIAG)
ERROR ILK_RX_LNEX_INT(6)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state
mismatches
ERROR ILK_RX_LNEX_INT(6)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.
ERROR ILK_RX_LNEX_INT(6)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'
(healthy) to a '0' (problem)
ERROR ILK_RX_LNEX_INT(6)[STAT_CNT_OVFL]: Rx lane statistic counter overflow
ERROR ILK_RX_LNEX_INT(6)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches
the burst control unit (as deonted by
ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
packets will receive an error.
ERROR ILK_RX_LNEX_INT(7)[SERDES_LOCK_LOSS]: Rx SERDES loses lock
ERROR ILK_RX_LNEX_INT(7)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will
automatically attempt to regain word boundary sync
ERROR ILK_RX_LNEX_INT(7)[CRC32_ERR]: Diagnostic CRC32 errors
ERROR ILK_RX_LNEX_INT(7)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of
(SYNC,SCRAM,SKIP,DIAG)
ERROR ILK_RX_LNEX_INT(7)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state
mismatches
ERROR ILK_RX_LNEX_INT(7)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.
ERROR ILK_RX_LNEX_INT(7)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'
(healthy) to a '0' (problem)
ERROR ILK_RX_LNEX_INT(7)[STAT_CNT_OVFL]: Rx lane statistic counter overflow
ERROR ILK_RX_LNEX_INT(7)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches
the burst control unit (as deonted by
ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open
packets will receive an error.
ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)
ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)
ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)
ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)
ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)
ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)
ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow
ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written
In MII/RGMII, one bit per port
TX Stats are corrupted
ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error
ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow
This interrupt should never assert
ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface
ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow
ERROR LMCX_INT(3)[SEC_ERR]: Single Error (corrected) of Rd Data
[0] corresponds to DQ[63:0]_c0_p0
[1] corresponds to DQ[63:0]_c0_p1
[2] corresponds to DQ[63:0]_c1_p0
[3] corresponds to DQ[63:0]_c1_p1
where _cC_pP denotes cycle C and phase P
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(3)[NXM_WR_ERR]: Write to non-existent memory
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(3)[DED_ERR]: Double Error detected (DED) of Rd Data
[0] corresponds to DQ[63:0]_c0_p0
[1] corresponds to DQ[63:0]_c0_p1
[2] corresponds to DQ[63:0]_c1_p0
[3] corresponds to DQ[63:0]_c1_p1
where _cC_pP denotes cycle C and phase P
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(2)[SEC_ERR]: Single Error (corrected) of Rd Data
[0] corresponds to DQ[63:0]_c0_p0
[1] corresponds to DQ[63:0]_c0_p1
[2] corresponds to DQ[63:0]_c1_p0
[3] corresponds to DQ[63:0]_c1_p1
where _cC_pP denotes cycle C and phase P
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(2)[NXM_WR_ERR]: Write to non-existent memory
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(2)[DED_ERR]: Double Error detected (DED) of Rd Data
[0] corresponds to DQ[63:0]_c0_p0
[1] corresponds to DQ[63:0]_c0_p1
[2] corresponds to DQ[63:0]_c1_p0
[3] corresponds to DQ[63:0]_c1_p1
where _cC_pP denotes cycle C and phase P
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(1)[SEC_ERR]: Single Error (corrected) of Rd Data
[0] corresponds to DQ[63:0]_c0_p0
[1] corresponds to DQ[63:0]_c0_p1
[2] corresponds to DQ[63:0]_c1_p0
[3] corresponds to DQ[63:0]_c1_p1
where _cC_pP denotes cycle C and phase P
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(1)[NXM_WR_ERR]: Write to non-existent memory
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(1)[DED_ERR]: Double Error detected (DED) of Rd Data
[0] corresponds to DQ[63:0]_c0_p0
[1] corresponds to DQ[63:0]_c0_p1
[2] corresponds to DQ[63:0]_c1_p0
[3] corresponds to DQ[63:0]_c1_p1
where _cC_pP denotes cycle C and phase P
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data
[0] corresponds to DQ[63:0]_c0_p0
[1] corresponds to DQ[63:0]_c0_p1
[2] corresponds to DQ[63:0]_c1_p0
[3] corresponds to DQ[63:0]_c1_p1
where _cC_pP denotes cycle C and phase P
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory
Write of 1 will clear the corresponding error bit
ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data
[0] corresponds to DQ[63:0]_c0_p0
[1] corresponds to DQ[63:0]_c0_p1
[2] corresponds to DQ[63:0]_c1_p0
[3] corresponds to DQ[63:0]_c1_p1
where _cC_pP denotes cycle C and phase P
Write of 1 will clear the corresponding error bit
ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred
ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred
ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write
Set when L2C_VRT_MEM blocked a store.
ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range
Set when a L2C_VRT_CTL[NUMID] violation blocked a
store.
ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range
Set when a L2C_VRT_CTL[MEMSZ] violation blocked a
store.
L2C_VRT_CTL[OOBERR] must be set for L2C to set this.
ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error
Whenever an L2C_VRT_MEM read finds a parity error,
that L2C_VRT_MEM cannot cause stores to be blocked.
Software should correct the error.
ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred
ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred
ERROR L2C_TADX_INT(1)[L2DSBE]: L2D Single-Bit Error
Shadow copy of L2C_ERR_TDTX[SBE]
Writes of 1 also clear L2C_ERR_TDTX[SBE]
ERROR L2C_TADX_INT(1)[L2DDBE]: L2D Double-Bit Error
Shadow copy of L2C_ERR_TDTX[DBE]
Writes of 1 also clear L2C_ERR_TDTX[DBE]
ERROR L2C_TADX_INT(1)[TAGSBE]: TAG Single-Bit Error
Shadow copy of L2C_ERR_TTGX[SBE]
Writes of 1 also clear L2C_ERR_TTGX[SBE]
ERROR L2C_TADX_INT(1)[TAGDBE]: TAG Double-Bit Error
Shadow copy of L2C_ERR_TTGX[DBE]
Writes of 1 also clear L2C_ERR_TTGX[DBE]
ERROR L2C_TADX_INT(1)[VBFSBE]: VBF Single-Bit Error
Shadow copy of L2C_ERR_TDTX[VSBE]
Writes of 1 also clear L2C_ERR_TDTX[VSBE]
ERROR L2C_TADX_INT(1)[VBFDBE]: VBF Double-Bit Error
Shadow copy of L2C_ERR_TDTX[VDBE]
Writes of 1 also clear L2C_ERR_TDTX[VDBE]
ERROR L2C_TADX_INT(1)[NOWAY]: No way available interrupt
Shadow copy of L2C_ERR_TTGX[NOWAY]
Writes of 1 also clear L2C_ERR_TTGX[NOWAY]
ERROR L2C_TADX_INT(1)[RDDISLMC]: Illegal Read to Disabled LMC Error
A DRAM read arrived before the LMC(s) were enabled
ERROR L2C_TADX_INT(1)[WRDISLMC]: Illegal Write to Disabled LMC Error
A DRAM write arrived before the LMC(s) were enabled
ERROR L2C_ERR_TDTX(1)[VSBE]: VBF Single-Bit error has occurred
ERROR L2C_ERR_TDTX(1)[VDBE]: VBF Double-Bit error has occurred
ERROR L2C_ERR_TDTX(1)[SBE]: L2D Single-Bit error has occurred
ERROR L2C_ERR_TDTX(1)[DBE]: L2D Double-Bit error has occurred
ERROR L2C_ERR_TTGX(1)[NOWAY]: No way was available for allocation.
L2C sets NOWAY during its processing of a
transaction whenever it needed/wanted to allocate
a WAY in the L2 cache, but was unable to. NOWAY==1
is (generally) not an indication that L2C failed to
complete transactions. Rather, it is a hint of
possible performance degradation. (For example, L2C
must read-modify-write DRAM for every transaction
that updates some, but not all, of the bytes in a
cache block, misses in the L2 cache, and cannot
allocate a WAY.) There is one "failure" case where
L2C will set NOWAY: when it cannot leave a block
locked in the L2 cache as part of a LCKL2
transaction.
ERROR L2C_ERR_TTGX(1)[SBE]: Single-Bit ECC error
ERROR L2C_ERR_TTGX(1)[DBE]: Double-Bit ECC error
ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error
Shadow copy of L2C_ERR_TDTX[SBE]
Writes of 1 also clear L2C_ERR_TDTX[SBE]
ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error
Shadow copy of L2C_ERR_TDTX[DBE]
Writes of 1 also clear L2C_ERR_TDTX[DBE]
ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error
Shadow copy of L2C_ERR_TTGX[SBE]
Writes of 1 also clear L2C_ERR_TTGX[SBE]
ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error
Shadow copy of L2C_ERR_TTGX[DBE]
Writes of 1 also clear L2C_ERR_TTGX[DBE]
ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error
Shadow copy of L2C_ERR_TDTX[VSBE]
Writes of 1 also clear L2C_ERR_TDTX[VSBE]
ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error
Shadow copy of L2C_ERR_TDTX[VDBE]
Writes of 1 also clear L2C_ERR_TDTX[VDBE]
ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt
Shadow copy of L2C_ERR_TTGX[NOWAY]
Writes of 1 also clear L2C_ERR_TTGX[NOWAY]
ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read to Disabled LMC Error
A DRAM read arrived before the LMC(s) were enabled
ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error
A DRAM write arrived before the LMC(s) were enabled
ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred
ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred
ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred
ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred
ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.
L2C sets NOWAY during its processing of a
transaction whenever it needed/wanted to allocate
a WAY in the L2 cache, but was unable to. NOWAY==1
is (generally) not an indication that L2C failed to
complete transactions. Rather, it is a hint of
possible performance degradation. (For example, L2C
must read-modify-write DRAM for every transaction
that updates some, but not all, of the bytes in a
cache block, misses in the L2 cache, and cannot
allocate a WAY.) There is one "failure" case where
L2C will set NOWAY: when it cannot leave a block
locked in the L2 cache as part of a LCKL2
transaction.
ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error
ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error
ERROR L2C_TADX_INT(3)[L2DSBE]: L2D Single-Bit Error
Shadow copy of L2C_ERR_TDTX[SBE]
Writes of 1 also clear L2C_ERR_TDTX[SBE]
ERROR L2C_TADX_INT(3)[L2DDBE]: L2D Double-Bit Error
Shadow copy of L2C_ERR_TDTX[DBE]
Writes of 1 also clear L2C_ERR_TDTX[DBE]
ERROR L2C_TADX_INT(3)[TAGSBE]: TAG Single-Bit Error
Shadow copy of L2C_ERR_TTGX[SBE]
Writes of 1 also clear L2C_ERR_TTGX[SBE]
ERROR L2C_TADX_INT(3)[TAGDBE]: TAG Double-Bit Error
Shadow copy of L2C_ERR_TTGX[DBE]
Writes of 1 also clear L2C_ERR_TTGX[DBE]
ERROR L2C_TADX_INT(3)[VBFSBE]: VBF Single-Bit Error
Shadow copy of L2C_ERR_TDTX[VSBE]
Writes of 1 also clear L2C_ERR_TDTX[VSBE]
ERROR L2C_TADX_INT(3)[VBFDBE]: VBF Double-Bit Error
Shadow copy of L2C_ERR_TDTX[VDBE]
Writes of 1 also clear L2C_ERR_TDTX[VDBE]
ERROR L2C_TADX_INT(3)[NOWAY]: No way available interrupt
Shadow copy of L2C_ERR_TTGX[NOWAY]
Writes of 1 also clear L2C_ERR_TTGX[NOWAY]
ERROR L2C_TADX_INT(3)[RDDISLMC]: Illegal Read to Disabled LMC Error
A DRAM read arrived before the LMC(s) were enabled
ERROR L2C_TADX_INT(3)[WRDISLMC]: Illegal Write to Disabled LMC Error
A DRAM write arrived before the LMC(s) were enabled
ERROR L2C_ERR_TDTX(3)[VSBE]: VBF Single-Bit error has occurred
ERROR L2C_ERR_TDTX(3)[VDBE]: VBF Double-Bit error has occurred
ERROR L2C_ERR_TDTX(3)[SBE]: L2D Single-Bit error has occurred
ERROR L2C_ERR_TDTX(3)[DBE]: L2D Double-Bit error has occurred
ERROR L2C_ERR_TTGX(3)[NOWAY]: No way was available for allocation.
L2C sets NOWAY during its processing of a
transaction whenever it needed/wanted to allocate
a WAY in the L2 cache, but was unable to. NOWAY==1
is (generally) not an indication that L2C failed to
complete transactions. Rather, it is a hint of
possible performance degradation. (For example, L2C
must read-modify-write DRAM for every transaction
that updates some, but not all, of the bytes in a
cache block, misses in the L2 cache, and cannot
allocate a WAY.) There is one "failure" case where
L2C will set NOWAY: when it cannot leave a block
locked in the L2 cache as part of a LCKL2
transaction.
ERROR L2C_ERR_TTGX(3)[SBE]: Single-Bit ECC error
ERROR L2C_ERR_TTGX(3)[DBE]: Double-Bit ECC error
ERROR L2C_TADX_INT(2)[L2DSBE]: L2D Single-Bit Error
Shadow copy of L2C_ERR_TDTX[SBE]
Writes of 1 also clear L2C_ERR_TDTX[SBE]
ERROR L2C_TADX_INT(2)[L2DDBE]: L2D Double-Bit Error
Shadow copy of L2C_ERR_TDTX[DBE]
Writes of 1 also clear L2C_ERR_TDTX[DBE]
ERROR L2C_TADX_INT(2)[TAGSBE]: TAG Single-Bit Error
Shadow copy of L2C_ERR_TTGX[SBE]
Writes of 1 also clear L2C_ERR_TTGX[SBE]
ERROR L2C_TADX_INT(2)[TAGDBE]: TAG Double-Bit Error
Shadow copy of L2C_ERR_TTGX[DBE]
Writes of 1 also clear L2C_ERR_TTGX[DBE]
ERROR L2C_TADX_INT(2)[VBFSBE]: VBF Single-Bit Error
Shadow copy of L2C_ERR_TDTX[VSBE]
Writes of 1 also clear L2C_ERR_TDTX[VSBE]
ERROR L2C_TADX_INT(2)[VBFDBE]: VBF Double-Bit Error
Shadow copy of L2C_ERR_TDTX[VDBE]
Writes of 1 also clear L2C_ERR_TDTX[VDBE]
ERROR L2C_TADX_INT(2)[NOWAY]: No way available interrupt
Shadow copy of L2C_ERR_TTGX[NOWAY]
Writes of 1 also clear L2C_ERR_TTGX[NOWAY]
ERROR L2C_TADX_INT(2)[RDDISLMC]: Illegal Read to Disabled LMC Error
A DRAM read arrived before the LMC(s) were enabled
ERROR L2C_TADX_INT(2)[WRDISLMC]: Illegal Write to Disabled LMC Error
A DRAM write arrived before the LMC(s) were enabled
ERROR L2C_ERR_TDTX(2)[VSBE]: VBF Single-Bit error has occurred
ERROR L2C_ERR_TDTX(2)[VDBE]: VBF Double-Bit error has occurred
ERROR L2C_ERR_TDTX(2)[SBE]: L2D Single-Bit error has occurred
ERROR L2C_ERR_TDTX(2)[DBE]: L2D Double-Bit error has occurred
ERROR L2C_ERR_TTGX(2)[NOWAY]: No way was available for allocation.
L2C sets NOWAY during its processing of a
transaction whenever it needed/wanted to allocate
a WAY in the L2 cache, but was unable to. NOWAY==1
is (generally) not an indication that L2C failed to
complete transactions. Rather, it is a hint of
possible performance degradation. (For example, L2C
must read-modify-write DRAM for every transaction
that updates some, but not all, of the bytes in a
cache block, misses in the L2 cache, and cannot
allocate a WAY.) There is one "failure" case where
L2C will set NOWAY: when it cannot leave a block
locked in the L2 cache as part of a LCKL2
transaction.
ERROR L2C_ERR_TTGX(2)[SBE]: Single-Bit ECC error
ERROR L2C_ERR_TTGX(2)[DBE]: Double-Bit ECC error
ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.
ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.
ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.
ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.
ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes
negative.
ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and
the count available is greater than pointers
present in the FPA.
ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in
the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes
negative.
ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and
the count available is greater than pointers
present in the FPA.
ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in
the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes
negative.
ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and
the count available is greater than than pointers
present in the FPA.
ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in
the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes
negative.
ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and
the count available is greater than than pointers
present in the FPA.
ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in
the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes
negative.
ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and
the count available is greater than than pointers
present in the FPA.
ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in
the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes
negative.
ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and
the count available is greater than than pointers
present in the FPA.
ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in
the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes
negative.
ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and
the count available is greater than than pointers
present in the FPA.
ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in
the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes
negative.
ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and
the count available is greater than than pointers
present in the FPA.
ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in
the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to
FPA_POOL0_THRESHOLD[THRESH] and a pointer is
allocated or de-allocated.
ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to
FPA_POOL1_THRESHOLD[THRESH] and a pointer is
allocated or de-allocated.
ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to
FPA_POOL2_THRESHOLD[THRESH] and a pointer is
allocated or de-allocated.
ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to
FPA_POOL3_THRESHOLD[THRESH] and a pointer is
allocated or de-allocated.
ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to
FPA_POOL4_THRESHOLD[THRESH] and a pointer is
allocated or de-allocated.
ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to
FPA_POOL5_THRESHOLD[THRESH] and a pointer is
allocated or de-allocated.
ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to
FPA_POOL6_THRESHOLD[THRESH] and a pointer is
allocated or de-allocated.
ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to
FPA_POOL7_THRESHOLD[THRESH] and a pointer is
allocated or de-allocated.
ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.
ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.
ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.
ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.
ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.
ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.
ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.
ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.
ERROR FPA_INT_SUM[FREE8]: When a pointer for POOL8 is freed bit is set.
ERROR FPA_INT_SUM[Q8_UND]: Set when a Queue8 page count available goes
negative.
ERROR FPA_INT_SUM[Q8_COFF]: Set when a Queue8 stack end tag is present and
the count available is greater than than pointers
present in the FPA.
ERROR FPA_INT_SUM[Q8_PERR]: Set when a Queue8 pointer read from the stack in
the L2C does not have the FPA owner ship bit set.
ERROR FPA_INT_SUM[POOL8TH]: Set when FPA_QUE8_AVAILABLE is equal to
FPA_POOL8_THRESHOLD[THRESH] and a pointer is
allocated or de-allocated.
ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the
address range for a pool specified by
FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.
ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed
ERROR ZIP_INT_REG[IBSBE]: IBUF Single Bit Error
ERROR ZIP_INT_REG[IBDBE]: IBUF Double Bit Error
ERROR ZIP_INT_REG[DOORBELL0]: Doorbell 0 count has overflowed
ERROR ZIP_INT_REG[DOORBELL1]: Doorbell 1 count has overflowed
ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits
[31:0] of the PBM memory.
NOT USED ON o68.
ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits
[63:32] of the PBM memory.
NOT USED ON o68.
ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits
[95:64] of the PBM memory.
NOT USED ON o68.
ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits
[127:96] of the PBM memory.
NOT USED ON o68.
ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a
supplied illegal value.
ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.
ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.
ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB
collides.
ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB
collides.
ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.
ERROR IPD_INT_SUM[SOP]: Set when a SOP is followed by an SOP for the same
reasm-id for a packet.
The first detected error associated with bits [14:12]
of this register will only be set here. A new bit
can be set when the previous reported bit is cleared.
Also see IPD_PKT_ERR.
ERROR IPD_INT_SUM[EOP]: Set when a EOP is followed by an EOP for the same
reasm-id for a packet.
The first detected error associated with bits [14:12]
of this register will only be set here. A new bit
can be set when the previous reported bit is cleared.
Also see IPD_PKT_ERR.
ERROR IPD_INT_SUM[DAT]: Set when a data arrives before a SOP for the same
reasm-id for a packet.
The first detected error associated with bits [14:12]
of this register will only be set here. A new bit
can be set when the previous reported bit is cleared.
Also see IPD_PKT_ERR.
ERROR IPD_INT_SUM[PW0_SBE]: Packet memory 0 had ECC SBE.
ERROR IPD_INT_SUM[PW0_DBE]: Packet memory 0 had ECC DBE.
ERROR IPD_INT_SUM[PW1_SBE]: Packet memory 1 had ECC SBE.
ERROR IPD_INT_SUM[PW1_DBE]: Packet memory 1 had ECC DBE.
ERROR IPD_INT_SUM[PW2_SBE]: Packet memory 2 had ECC SBE.
ERROR IPD_INT_SUM[PW2_DBE]: Packet memory 2 had ECC DBE.
ERROR IPD_INT_SUM[PW3_SBE]: Packet memory 3 had ECC SBE.
ERROR IPD_INT_SUM[PW3_DBE]: Packet memory 3 had ECC DBE.
ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed
ERROR TIM_INT0[INT0]: Interrupt bit per ring. Each bit indicates the
ring number in error. Each bit in this reg is set
regardless of TIM_INT0_EN value.
ERROR TIM_INT_ECCERR[SBE]: TIM RDS memory had a Single Bit Error
ERROR TIM_INT_ECCERR[DBE]: TIM RDS memory had a Double Bit Error
ERROR SSO_ERR[IOP]: Illegal operation errors
ERROR SSO_ERR[FIDX_DBE]: Double bit error for FIDX RAM
ERROR SSO_ERR[IDX_SBE]: Single bit error for IDX RAM
ERROR SSO_ERR[PND_DBE0]: Double bit error for even PND RAM
ERROR SSO_ERR[OTH_SBE1]: Single bit error for odd OTH RAM
ERROR SSO_ERR[OTH_DBE1]: Double bit error for odd OTH RAM
ERROR SSO_ERR[OTH_SBE0]: Single bit error for even OTH RAM
ERROR SSO_ERR[OTH_DBE0]: Double bit error for even OTH RAM
ERROR SSO_ERR[PND_SBE1]: Single bit error for odd PND RAM
ERROR SSO_ERR[PND_DBE1]: Double bit error for odd PND RAM
ERROR SSO_ERR[PND_SBE0]: Single bit error for even PND RAM
ERROR SSO_ERR[FPE]: Free page error
ERROR SSO_ERR[AWE]: Out-of-memory error (ADDWQ Request is dropped)
ERROR SSO_ERR[BFP]: Bad Fill Packet error
Last byte of the fill packet did not match 8'h1a
ERROR SSO_ERR[IDX_DBE]: Double bit error for IDX RAM
ERROR SSO_ERR[FIDX_SBE]: Single bit error for FIDX RAM
ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete
within 0xffff core clocks.
ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit
ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive
read-data/commit in 0xffff core clocks.
ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.
ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit
ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.
This occurs when the BAR 0 address space is
disabeled.
ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register
from MAC 0. This occurs when the window registers
are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.
This occurs when the BAR 0 address space is
disabeled.
ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register
from MAC 0. This occurs when the window registers
are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.
This occurs when the BAR 0 address space is
disabeled.
ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register
from MAC 1. This occurs when the window registers
are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.
This occurs when the BAR 0 address space is
disabeled.
ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register
from MAC 1. This occurs when the window registers
are disabeld and a window register access occurs.
ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which
doorbell can be found in DPI_PINT_INFO[PIDBOF]
ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which
doorbell can be found in DPI_PINT_INFO[PSLDBOF]
ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit
set.
ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list
read this bit is set.
ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read
this bit is set.
ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter
pointer pair this bit is set.
ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction
this bit is set.
ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0
this bit is set.
ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1
this bit is set.
ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress
range of the Packet-CSR, but for an unused
address.
ERROR PEXP_SLI_INT_SUM[PIPE_ERR]: Set when a PIPE value outside range is received.
ERROR KEY_INT_SUM[KED0_SBE]: Error Bit
ERROR KEY_INT_SUM[KED0_DBE]: Error Bit
ERROR KEY_INT_SUM[KED1_SBE]: Error Bit
ERROR KEY_INT_SUM[KED1_DBE]: Error Bit
ERROR PIP_INT_REG[PRTNXA]: Non-existent port
ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD
ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper
This interrupt can occur with received PARTIAL
packets that are truncated to SKIP bytes or
smaller.
ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])
ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory
ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory
ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC
stripping in IPD is enable
ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit
When set, the 20b accumulated doorbell register
had overflowed (SW wrote too many doorbell requests).
If the DBLINA had previously been enabled(set),
an interrupt will be posted. Software can clear
the interrupt by writing a 1 to this register bit.
NOTE: Detection of a Doorbell Register overflow
is a catastrophic error which may leave the DFA
HW in an unrecoverable state.
ERROR DFA_ERROR[DC0PERR]: Cluster#0 RAM[3:1] Parity Error Detected
See also DFA_DTCFADR register which contains the
failing addresses for the internal node cache RAMs.
ERROR DFA_ERROR[DC1PERR]: Cluster#1 RAM[3:1] Parity Error Detected
See also DFA_DTCFADR register which contains the
failing addresses for the internal node cache RAMs.
ERROR DFA_ERROR[DC2PERR]: Cluster#2 RAM[3:1] Parity Error Detected
See also DFA_DTCFADR register which contains the
failing addresses for the internal node cache RAMs.
ERROR DFA_ERROR[DLC0_OVFERR]: DLC0 Fifo Overflow Error Detected
This condition should NEVER architecturally occur, and
is here in case HW credit/debit scheme is not working.
ERROR DFA_ERROR[DLC1_OVFERR]: DLC1 Fifo Overflow Error Detected
This condition should NEVER architecturally occur, and
is here in case HW credit/debit scheme is not working.
ERROR DFA_ERROR[DFANXM]: DFA Non-existent Memory Access
For o68: DTEs (and backdoor CSR DFA Memory REGION reads)
have access to the following 38bit L2/DRAM address space
which maps to a 37bit physical DDR3 SDRAM address space.
see:
DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF
maps to lower 256MB of physical DDR3 SDRAM
DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF
maps to upper 127.75GB of DDR3 SDRAM
L2/DRAM address space Physical DDR3 SDRAM Address space
(38bit address) (37bit address)
+-----------+ 0x0020.0FFF.FFFF
|
=== DR1 === +-----------+ 0x001F.FFFF.FFFF
(128GB-256MB)| | |
| | => | | (128GB-256MB)
+-----------+ 0x0000.1FFF.FFFF | DR1
256MB | HOLE | (DO NOT USE) |
+-----------+ 0x0000.0FFF.FFFF +-----------+ 0x0000.0FFF.FFFF
256MB | DR0 | | DR0 | (256MB)
+-----------+ 0x0000.0000.0000 +-----------+ 0x0000.0000.0000
In the event the DFA generates a reference to the L2/DRAM
address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to
an address above 0x0020.0FFF.FFFF, the DFANXM programmable
interrupt bit will be set.
SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR
accesses to DFA Memory REGION MUST avoid making references
to these non-existent memory regions.
NOTE: If DFANXM is set during a DFA Graph Walk operation,
then the walk will prematurely terminate with RWORD0[REA]=ERR.
If DFANXM is set during a NCB-Direct CSR read access to DFA
Memory REGION, then the CSR read response data is forced to
128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW
being accessed, either the upper or lower QW will be returned).
ERROR DFA_ERROR[REPLERR]: DFA Illegal Replication Factor Error
For o68: DFA only supports 1x, 2x, and 4x port replication.
Legal configurations for memory are to support 2 port or
4 port configurations.
The REPLERR interrupt will be set in the following illegal
configuration cases:
1) An 8x replication factor is detected for any memory reference.
2) A 4x replication factor is detected for any memory reference
when only 2 memory ports are enabled.
NOTE: If REPLERR is set during a DFA Graph Walk operation,
then the walk will prematurely terminate with RWORD0[REA]=ERR.
If REPLERR is set during a NCB-Direct CSR read access to DFA
Memory REGION, then the CSR read response data is UNPREDICTABLE.
ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer
ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed
ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0
ERROR PKO_REG_ERROR[LOOPBACK]: A packet was sent to an illegal loopback port
ERROR DPI_INT_REG[NDERR]: NCB Decode Error
DPI received a NCB transaction on the outbound
bus to the DPI deviceID, but the command was not
recognized.
ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow
DPI can store upto 16 CSR request. The FIFO will
overflow if that number is exceeded.
ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.
DPI has a 32-bit counter for each request's queue
outstanding doorbell counts. Interrupt will fire
if the count overflows.
ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer
Interrupt will fire if DPI forms an instruction
fetch to the NULL pointer.
ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length
Interrupt will fire if DPI forms an instruction
fetch with length of zero.
ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow
DPI tracks outstanding instructions fetches.
Interrupt will fire when FIFO overflows.
ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow
DPI tracks outstanding instructions fetches.
Interrupt will fire when FIFO underflows.
ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction
Fetched instruction word was 0.
ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer
Next pointer was NULL.
ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill
Instruction fill when none outstanding.
ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or
destination port was in reset.
this bit is set.
ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or
destination port was in reset.
this bit is set.
ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from
the I/O subsystem.
ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an
ErrorResponse from the I/O subsystem.
SW must clear the bit before the the cooresponding
instruction queue will continue processing
instructions if DPI_REQ_ERR_RSP_EN[EN] is set.
ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an
instruction because the source or destination
was in reset.
SW must clear the bit before the the cooresponding
instruction queue will continue processing
instructions if DPI_REQ_ERR_RST_EN[EN] is set.
ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while
MIO_RST_CTL0[RST_LINK]=0. Software must assert
then de-assert CIU_SOFT_PRST[SOFT_PRST]
ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while
MIO_RST_CTL1[RST_LINK]=0. Software must assert
then de-assert CIU_SOFT_PRST1[SOFT_PRST]
ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1
and MIO_RST_CTL0[RST_CHIP]=0
ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1
and MIO_RST_CTL1[RST_CHIP]=0
ERROR SSO_IQ_INT[IQ_INT]: Input queue interrupt bits
ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution
ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state
ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot
ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot
ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a
fatal error.
ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error
ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error
ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full
ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full
ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full
ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full
ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full
ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty
ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error
When the error happenes, the whole NCB system needs
to be reset.
ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error
When the error happenes, the whole NCB system needs
to be reset.
WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure. WARNING: FIX_IPD_PTR_ALIGNMENT get_work() timeout occurred. WARNING: FIX_IPD_PTR_ALIGNMENT failed. FP F F F G GH F E KX K K K L LP K JWQE Buffers \ ] ] ] ] ] ]H ^ERROR: %s: Invalid interface
ERROR: %s: Reserving L1 PQ
ERROR: %s: Configuring L1 PQ
ERROR: %s: allocation L2 SQ
ERROR: %s: Failed channel queues
ERR-SQ/ ERROR: %s: allocating %s
ERROR: %s: configuring %s
ERROR: %s: level sequence error
WARNING: %s: DQ# %u not integral of 8
ERROR: %s: configuring queues for xiface %u:%u chan %u
WARNING: %s: xiface %#x misconfigured
ERROR: %s: Invalid interface %u:%u
ERROR %s: xiface %u:%u/%u failed allocation L1 PQ
ERROR %s: Configuring L1 PQ
ERROR: %s: could not reserve DQs
ERROR: %s: No IPD port for interface %d port %d
ERROR: %s: No descriptor queues for interface %d port %d
WARNING: %s: PKO buffer deficit %d
ERROR: %s: invalid iface %u:%u
ERROR: %s: allocation L1 PQ
ERROR: %s: Configuring %s
ERROR: %s: Configuring %s for PFC
WARNING: %s: option set failed on iface %u:%u/%u
ERROR: %s: failed on iface %u:%u/%u
ERROR: %s:failed block initialization
ERROR: %s: creating NULL interface
PKO3 AURA ERROR: %s: PKO3 memory allocation error
ERROR: %s: failed to start PPKO
ERROR: %s AURA create failed
ERROR: %s: FPA failure AURA=%u:%d
ERROR: %s: No DQs for iface %u:%d/%u
ERROR: %s: failed to unregister DQs iface %u/%d/%u
ERROR: %s: querying queue %u
ERROR: %s: closing queue %u
__cvmx_pko3_config_gen_interface __cvmx_pko3_helper_dqs_activate __cvmx_pko3_helper_dqs_activate cvmx_helper_pko3_init_interface __cvmx_pko3_config_chan_interface __cvmx_pko3_config_chan_interface __cvmx_pko3_config_pfc_interface __cvmx_helper_pko3_init_global cvmx_helper_pko3_init_global cvmx_helper_pko3_init_global __cvmx_pko3_config_memory cvmx_helper_pko3_shut_interface ERROR: Unsupported Octeon model in %s
__cvmx_helper_rgmii_probe PCIe: Port %d shutdown timeout
%d:PCIe: Port %d is SRIO, skipping.
%d:PCIe: Port %d is SGMII, skipping.
%d:PCIe: Port %d is XAUI, skipping.
%d:PCIe: Port %d is ILK, skipping.
%d:PCIe: Port %d is unknown, skipping.
%d:PCIe: Port %d in endpoint mode.
/soc cavium,connected-pcie-reset-2x1 %d:PCIe: BIST FAILED for port %d (0x%016llx)
%d:PCIe: BIST2 FAILED for port %d (0x%016llx)
PCIe: Link timeout on port %d, probably the slot is empty
PCIe: Port %d link active, %d lanes, speed gen%d
%d:PCIe: Port %d stuck in reset, skipping.
%s: ERROR: too many segments
PKO Undefined error WARNING: AURA vs PKO node mismatch WARNING: %s: PKO already enabled on node %u
ERROR: %s: PKO DFPI failed, PKO_STATUS=%#llx DPFI_STATUS=%#llx
%s: ERROR: interface %d:%u port %d has no MAC %d/%d
ERROR: %s: failed, PKO_STATUS=%#llx
%s: ERROR: timeout waiting for PKO3 ptr flush
%s: ERROR: Failed to open dq :%u: %s
WARNING: %s: Failed to close dq :%u: %s
DEBUG: %s: dq %u depth %u
%s: ERROR: Failed to query dq :%u: %s
%s: DEBUG: dq %u depth %u
ERROR: %s: invalid interface %u:%u/%u
ERROR: %s: unused interface %u:%u/%u
PKO3 FIFO number does not match MAC
%s: FIFO %d failed to drain
%s: ERROR: invalid WQE
ERROR: %s: subcommand restriction violated
ERROR: %s: Only one SEND_WORK_S is allowed
No error PKO queue not ready PKO failed to allocate buffer from FPA PKO out of buffers PKO failed to return buffer to FPA PKO queue already opened PKO queue has not been created PKO queue is not empty Illegal PKO command construct h @ H h cvmx_pko3_hw_init_global cvmx_pko_setup_macs cvmx_pko3_hw_disable cvmx_pko_dq_open __cvmx_pko3_do_dma cvmx_pko3_dq_close cvmx_pko3_dq_query cvmx_pko3_interface_options cvmx_pko3_port_xoff cvmx_pko3_pdesc_from_wqe cvmx_pko3_pdesc_subdc_add cvmx_pko3_pdesc_buf_append cvmx_pko3_pdesc_notify_wqe /opt/3.1.2j/OCTEON-SDK-3.1.2-p12-L3-603/executive/cvmx-profiler.c buffer_ptr != NULL event_config_block event_block eccb.cfg_blk.pcpu_base_addr[cpu] != NULL cvmx_get_memory_addr cvmx_init_pcpu_block SRIO%d: Config write addressing error (offset=0x%x)
SRIO%d: Pending bit stuck before config write
SRIO%d: Config write timeout
SRIO%d: Config read addressing error (offset=0x%x)
SRIO%d: Pending bit stuck before config read
SRIO%d: Config read timeout
SRIO%d: Config read data timeout
SRIO%d: Initialization called on a port not in SRIO mode
SRIO%d: Port in %s mode
host endpoint SRIO%d: Send doorbell destid=0x%x, priority=%d, data=0x%x
SRIO%d: Pending bit stuck before doorbell
SRIO%d: Send doorbell failed
SRIO%d: Receive doorbell sequence=0x%x, srcid=0x%x, priority=%d, data=0x%x
SRIO%d: Soft packet FIFO sending %d bytes %08x SRIO%d: Soft packet FIFO received %d bytes SRIO%d: Failed to map range 0x%llx-0x%llx spanning a 34bit boundary
SRIO%d: Attempt to map 16bit device ID 0x%x using 66bit addressing
SRIO%d: Attempt to map address 0x%llx using 66bit addressing
ERROR: %s: SRIO%d: Unable to find free SRIOX_S2M_TYPEX
SRIO: Unable to find free SLI_MEM_ACCESS_SUBIDX SRIO%d: Local write[0x%06x] => 0x%08x
SRIO%d: Remote write[id=0x%04x hop=%3d offset=0x%06x] => 0x%08x
SRIO%d: Local read [0x%06x] <= 0x%08x
SRIO%d: Remote read [id=0x%04x hop=%3d offset=0x%06x] <= 0x%08x
__cvmx_srio_alloc_s2m %s: attr %d out of range [0, %d)
ERROR: Invalid Octeon Attribute 0x%x
octeon_set_attr octeon_clear_attr ERROR: Software not configured for this chip
Expecting ID=0x%08x, Chip is 0x%08x
Refusing to run on older revision than program was compiled for.
################################################### WARNING: Software configured for older revision than running on.
Compiled for ID=0x%08x, Chip is 0x%08x
###################################################
XX DAP 66 68 F71 AAP CP F75 XXX SCP CCP 72 SP EXP NSP %d.%d SSP NSPB2 HAP 76 78 77 HCP 71 70 73 DSP %d%c %s%c CN%s%sp%s-%d-%s 80 85 88 90 0 t , p <
@
0
ـ
@
p
ڠ
@
` AGL%d: Timeout waiting for GMX to be idle
ERROR: %s: Invalid L1 PQ
ERROR: %s: Channel mapping failed
5L 7 6 6@ 6 5cvmcs_dcb_get_base_queues cvmcs_dcb_init_pko Error5: failed to allocate memory to timer wqe
Failed to allocate memory to Front
Error1: In %s
ERROR: The RX State Machine is broken!
Error in ' cvmcs_dcb_dcbx_rx_frame state ERROR: The TX State Machine is broken!
Error5: failed to allocate memory to LLDP frame
Error : In cvmcs_dcb_dcbx_tx_shutdown_frame
Error1:In %s
Failed to Create frame for port %d
ERROR The TX State Machine is broken!
Error : in dcbx_capability_update:
Failed to send dcbx cfg
Error : %s
LLDP state machines stopped for port %d
timer failled
F Gh F F G G( G@ G G Gh J Kh J J J KP K8 K0 K J T T U( U T T U U V U V VX V Ucvmcs_dcbx_auto_negotiation cvmcs_dcbx_tx_info_frame cvmcs_dcbx_set_tx_timers_state Error3:In dcbx_set_default_configure
Error4: In dcbx_set_default_configure
Error: In cvmcs_dcbx_ieee_asymmetric_st_machine
Error: Error: In %s
Frame validation failed:tlv count
Validation Ignored frame:ets rcmnd len
Validation ingnored frame:Total bw =%d
num_traffic_classes = %x
ets_flags = %x
pfc_flags = %x
priority_assignment_table = %d tc_bw_assignment_table = tsa_assignment_table = PfcEnable = %x
App priority tables = %d
Table[%d] selector = %d,priority = %d, protocol_id = %x
DCBX Version Mistmatch
DCBX Version Not Offloaded
g g gh gP g n n n n ncvmcs_dcbx_ieee_something_changed_remote cvmcs_dcbx_ieee_rx_process_frame Error: In dcbx_cee_Compatible function
Error: dcbx_cee_feat_sm_next is broken. state = %d
Error: dcbx_cee_feat_sm_run is broken. state = %d
Error: dcbx_cee_cntrl_sm_next is broken. state = %d
Error: dcbx_cee_cntrl_sm_run is broken. state = %d
In %s : shutdown frame
switch Defaultbad frame TLV_TYPE = %d
` ( ( ( ( ( ( ( ( ( h h H 0 X 0 h x x x 0 cvmcs_dcbx_cee_rx_process_frame ERROR %s : QCN RP FAST TIME add failed
ERROR %s : QCN RP ACTIVE TIME add failed
ERROR %s : QCN RP HYPER ACTIVE TIME add failed
ERROR %s : rp_byte_wqe allocation failed
ERROR %s : byte_data_pkt allocation failed
ERROR %s : rp_timer_wqe allocation failed
ERROR %s : timer_data_pkt allocation failed
ERROR %s : Invalid CNM-frame
cvmcs_dcb_qcn_main cvmcs_dcb_qcn_init_rp cvmcs_dcb_qcn_rp_fast_time cvmcs_dcb_qcn_rp_active_time cvmcs_dcb_qcn_rp_hyper_time %s(): %i: Error: Unknown Queue Type
%s(): %i: Error: sq depth fail
%s(): %i: Error: Memory is not allocated for subq_mem
%s(): %i: Error: Memory is not allocated for subq_cmnds_mem
%s(): %i: Error: CQ depth is less than mimimum queue entry size
%s(): %i: Error: Memory is not allocated for cq_mem
%s(): %i: Error: Memory is not allocated for cq_cmnds_mem
DEV_HOST_PG_SZ %s(): %i: List_DEV_HOST_PG_SZ Allocation failed
%s(): %i: multiple page sizes needed by hosts. not yet handled
%s(): %i: Error: Unsupported fid
%s(): %i: Error: Unsupproted fid
%s(): %i: Error npl_dma_create_first_pointers: First Pointer is NULL
%s(): %i: Error npl_dma_create_last_pointers: Last Pointer Address is NULL
%s(): %i: Pool ID: 0x%lx
%s(): %i: ..............
%s(): %i: Error: Asynchronous limit is set to zero :Can't handle async event updates from device
%s(): %i: Error: Max AeRl reached
%s(): %i: Error: Invalid QID
%s(): %i: Error: The queue not exists
%s(): %i: Error: sub queue associated to this cq exist
%s(): %i: Error: queue does not exist
%s(): %i: Error: Freed %d fused cmp cmds
%s(): %i: DMA ERROR: PRP_NULL ....wrong parameters
%s(): %i: First Addr= 0x%016lx
%s(): %i: Last Addr= 0x%016lx
%s(): %i: nbytes = 0x%x
%s(): %i: DMA_ERROR: ....PRP_NULL
%s(): %i: lastptr.prp1= 0x%016lx
%s(): %i: DMA_ERROR: PRP_NOLIST
%s(): %i: Error: npl_dma_submit
%s(): %i: DMA Error!!! DMA_BYTE_POINTER ..... wrong parameters
%s(): %i: DMA_ERROR: ....DMA_BYTE_POINTER
%s(): %i: DMA Error!!! DMA_ONLY_NONE ..... wrong parameters
%s(): %i: DMA_ERROR: ....DMA_ONLY_NONE
%s(): %i: DMA ERROR: PRP_NOLIST ....wrong parameters
%s(): %i: Error: process_logpage() SMART DMA failed
%s(): %i: Error: npl_process_logpage(): dma too slow or failed
%s(): %i: Error: process_logpage() dma has failed
%s(): %i: Error: process_logpage() SMART dma failed
%s(): %i: npl_process_logpage(): dma too slow or failed
%s(): %i: Bad Aligned PRP in prp-list
%s(): %i: Error: PRP List local DMA txfer has failed
%s(): %i: Error: Invalid NSID
%s(): %i: Invalid subcode in GET_STATS command
%s(): %i: Error: PRP1 is not valid
%s(): %i: Error: PRP2 is invalid
%s(): %i: Error: GET_STATS Admin Data transfer has failed
%s(): %i: Unknown identify request %d
%s(): %i: Error: Identify CMD Admin Data transfer has failed
%s(): %i: Error: queue size exceeded
%s(): %i: Error: Invalid Qid
%s(): %i: Error: PRP bad alignment
%s(): %i: Error: INVALID QID
%s(): %i: Error: invalid QID check
%s(): %i: Error: SQ %d memory allocation failed:
%s(): %i: Error: Queue size exceeded
%s(): %i: Error: DMA transfer failed
%s(): %i: Error: Invalid CQID
%s(): %i: Error: Invalid CQID
%s(): %i: Error: PRP Bad alignment
%s(): %i: Error: Invalid queue size: %d
%s(): %i: Error: Invalid cqid: %d
%s(): %i: Error: Queue with same qid already exists: %d
%s(): %i: Error: CQ %d memory allocation failed:
%s(): %i: Error: Queue size not supported
%s(): %i: Aborting outstanding async requests
%s(): %i: Controller %d disable: CC %x
%s(): %i: Controller %d disable done
%s(): %i: Controller %d abrupt shutdown: CC %x
%s(): %i: Controller %d abrupt shutdown done
%s(): %i: Controller %d normal shutdown: CC %x
%s(): %i: Controller %d normal shutdown done
%s(): %i: Controller %d enable: CC %x
%s(): %i: Controller %d enable failed
%s(): %i: Controller %d enable done: CC %x
%s(): %i: Error: DMA failure seen for sqid %u cmdid %u
%s(): %i:
DWORD%d :
%s(): %i: 0x%02x
%s(): %i:
%s(): %i: Error: DMA transfer has failed
%s(): %i: Command %d is in fly. Aborting
%s(): %i: Abort command: cmdid %d on VF %d SQ %d
%s(): %i: Command %d is not in SQ %d. Can't be aborted
%s(): %i: ERROR: Completion Queue entry Invalid
%s(): %i: Error:Process from cpl_list
%s(): %i: Error: Add Completion Entry DMA txfer has failed
%s(): %i: Command ID mismatch after sq fetch: vf %d old cmdid 0x%lx: New cmdid 0x%x
%s(): %i: Error: Invalid name space ID
%s(): %i: PRP1 bad alignment
%s(): %i: PRP2 bad alignment
%s(): %i: PRP2 List pointer alignment
%s(): %i: %s dma failure
%s(): %i: Err: lcmdid pool empty
%s(): %i: Err: lcmdid >= MAX_SQ_DEPTH
%s(): %i: Err: Trying to clear bit that is not set: SQID %d lcmdid %d
%s(): %i: Aborting cmd %d on VF %d SQ %d
%s(): %i: Completing abort cmdid %d on VF %d
%s(): %i: NQM interrrupt coalescing disabled
̘ P P P P P x P ̸ P x @ npl_controller_enable npl_abort_async_event_req npl_controller_configuration npl_controller_shutdown npl_alloc_block npl_create_admin_sub_queue npl_create_admin_cpl_queue npl_process_io_request npl_create_io_cq npl_create_io_sq npl_delete_io_sq npl_delete_io_cq npl_process_identify npl_process_get_stats npl_set_features npl_get_features npl_make_prp_list_local npl_process_io_data_transfer_tag npl_async_event_command npl_async_event_update npl_process_logpage npl_add_completion_queue_entry npl_dma_submit npl_dma_create_first_pointers npl_dma_create_last_pointers npl_fpa_alloc print_cmd_info_nbytes npl_xfer_discontiguous_cq_entries npl_abort_cmd_in_sq npl_abort_command npl_fetch_nvme_command npl_alloc_local_cmd_id npl_free_local_cmd_id npl_handle_aborted_cmd nvme_set_intr_coalescing_off %s(): %i: Could not allocate local commandID
%s(): %i: Error : Unknown Tag %x
%s(): %i: NVMe driver init:
%s(): %i: NVMe setting up minimal data buf pool
NVMe Data bufs
P
P
QH
Qx
Q
Q
R
R
R
P
Q nvme_process_wqe nvme_init %s(): %i: Error: io_cmd_context->data_bufs Mem alloc failed
%s(): %i: DMA Local buffers alloc failed
%s(): %i: Error: FPA alloc failed
%s(): %i: Error: LBA out of range
%s(): %i: Error: I/O Read Cmd Data transfer has failed, %lu bytes left
%s(): %i: Error: I/O Write Cmd Data transfer has failed, %lu bytes left
%s(): %i: Error: io_cmd_context->compare_bufs Mem alloc failed
%s(): %i: Error: dma_data_bufs Mem alloc failed
%s(): %i: Error: I/O Compare Datatransfer has failed, %lu bytes left
%s(): %i: Error: Unknown Command. Not Supported
%s(): %i: Error: ramdisk memory allocation failed, allocation: %ld
%s(): %i: Presenting Linux block disks alone as NVMe name spaces
%s(): %i: Cannot allocate namespace structure
sal_do_ramdisk_io sal_complete_ramdisk_io sal_init_store sal_init %s(): %i: Error:async_event::Memory Allocation Failure
%s(): %i: Error:nvme_stats_dma_mem: Memory Allocation Failure
%s(): %i: NVME dev mem alloc failed
%s(): %i: SQ struct mem alloc failed
%s(): %i: SQ cmds mem alloc failed
%s(): %i: CQ struct mem alloc failed
%s(): %i: CQ cmds mem alloc failed
%s(): %i: NS Mapping mode set to SATA only
@ @ }OCTNVME0000000000000OCTEON NVME 0.0.1 00.00.01OCT 0 fD nqm_dev_init nvme_config_init nvme_set_sata_only_map %s(): %i: Invalud vf_mode %d passed
%s(): %i: Setting vf_mode to %d
%s(): %i: Setting nqm sq credits to %d
%s(): %i: Setting nqm cplq size to %d
%s(): %i: Error: Cannot create vf %d
%s(): %i: Max supported vfs in nqm_vf_mode %u are %u
%s(): %i: VF value %u is out of range
%s(): %i: Improper update to vf %d %s. Status %lx
CQ SQ %s(): %i: vf %d is not active to post async logs
%s(): %i: CQ fatal error due to PRP read failure
%s(): %i: SQ fatal error due to PRP read failure
%s(): %i: Host changed the configuration of the vf %d admin %s while it is eabled
%s(): %i: FLR to nvme controller %d
%s(): %i: stop req bit set for PF2 vf-%d
%s(): %i: stop req bit set for PF 2
%s(): %i: NQM: PCIE_VF_ENABLE_CLR interrupt
%s(): %i: NQM: PCIE_MAC_RESET interrupt
%s(): %i: NQM: FPA_NO_PTRS interrupt
%s(): %i: NQM: CS DBE interrupt
%s(): %i: NQM: CS SBE interrupt
%s(): %i: NQM: NCB_TX_ERR interrupt
%s(): %i: NQM: HS DBE interrupt
%s(): %i: hs bist status is %x
%s(): %i: cs bist status is %x
%s(): %i: Exiting vf %d admin sq delete abruptly after timeout
%s(): %i: Exiting sq %d disable abruptly after timeout
%s(): %i: error amin cpl base address not 128 bit aligned
%s(): %i: Exiting vf %d admin cq delete abruptly after timeout
%s(): %i: Exiting cq %d disable abruptly after timeout
%s(): %i: NQM: Improper IV %d while creating IO CQ
%s(): %i: error cpl base addr not 128 bit aligned cqid %d
%s(): %i: Invalid IO CQID
%s(): %i: Exiting vf %d io cq %d delete abruptly after timeout
%s(): %i: Invalid IO SQID
%s(): %i: Exiting vfid %d iosq %d delete abruptly after qempty wait timeout
%s(): %i: Exiting vfid %d iosq %d delete abruptly after credit wait timeout
%s(): %i: NQM: Err: CPL submit: CPL queue deleted
%s(): %i: NQM_VF%d_CAP %lx
%s(): %i: NQM_VF%d_VS %x
%s(): %i: NQM_VF%d_INTMS %x
%s(): %i: NQM_VF%d_INTMC %x
%s(): %i: NQM_VF%d_CC %x
%s(): %i: NQM_VF%d_CSTS %x
%s(): %i: NQM_VF%d_NSSR %x
%s(): %i: NQM_VF%d_AQA %x
%s(): %i: NQM_VF%d_ASQ %lx
%s(): %i: NQM_VF%d_ACQ %lx
%s(): %i: NQM_VF%d_SQ%d_TDBL %x
%s(): %i: NQM_VF%d_CQ%d_HDBL %x
%s(): %i: NQM_VF%d_SQ%d_ENA %lx
%s(): %i: NQM_VF%d_SQ%d_CREDIT %lx
%s(): %i: NQM_VF%d_SQ%d_HEAD %lx
%s(): %i: NQM_VF%d_SQ%d_FC %lx
%s(): %i: NQM_VF%d_SQ%d_CC %lx
%s(): %i: NQM_VF%d_SQ%d_PRP %lx
%s(): %i: NQM_VF%d_SQ%d_BASE %lx
%s(): %i: NQM_VF%d_CQ%d_ENA %lx
%s(): %i: NQM_VF%d_ACQ_CC %lx
%s(): %i: NQM_VF%d_CPL%d_TDB %lx
%s(): %i: NQM_VF%d_SQ%d_SSO_SETUP %lx
%s(): %i: NQM_VF%d_CPL%d_BASE_ADDR_N_SZ %lx
%s(): %i: NQM_VF%d_CPL%d_H %lx
%s(): %i: NQM_VF%d_CPL%d_IFC %lx
%s(): %i: NQM_VF%d_CQ%d_TAIL %lx
%s(): %i: NQM_VF%d_CQ%d_PRP %lx
%s(): %i: NQM_VF%d_CQ%d_BASE %lx
%s(): %i: NQM_VF%d_CQ%d_CC %lx
%s(): %i: NQM_CS_ECC0_INT %lx
%s(): %i: NQM_CS_MEM_CTL0 %lx
%s(): %i: NQM_CS_BIST_STATUS0 %lx
%s(): %i: NQM_VF%d_INT %lx
%s(): %i: NQM_VF%d_INT_W1S %lx
%s(): %i: NQM_VF%d_INT_ENA_W1C %lx
%s(): %i: NQM_VF%d_INT_ENA_W1S %lx
%s(): %i: NQM_VF_MODE %lx
%s(): %i: NQM_IC_DIV %lx
%s(): %i: NQM_GLBL_TAG %lx
%s(): %i: NQM_CFG %lx
%s(): %i: NQM_FI_FPA_AURA %lx
%s(): %i: NQM_SCRATCH %lx
%s(): %i: NQM_CLKEN %lx
%s(): %i: NQM_HS_ECC0_INT %lx
%s(): %i: NQM_HS_MEM_CTL0 %lx
%s(): %i: NQM_HS_BIST_STATUS0 %lx
%s(): %i: NQM_INT %lx
%s(): %i: NQM_NCB_TX_ERR_WORD %lx
%s(): %i: NQM_NCB_TX_ERR_INFO %lx
%s(): %i: NQM_NCB_INT %lx
%s(): %i: NQM_VF%d_VEC%d_MSIX_ADDR %lx
%s(): %i: NQM_VF%d_VEC%d_MSIX_CTL %lx
%s(): %i: NQM_VF%d_MSIX_PBA %lx
%s(): %i: NQM_VF%d_IC_THR %lx
%s(): %i: NQM_VF%d_IC_TIME %lx
%s(): %i: NQM_MSIX_DBG_CI_SM %lx
%s(): %i: NQM_MSIX_DBG %lx
%s(): %i: NQM_VF%d_VEC%d_MSIX_CD %lx
%s(): %i: NQM_VF%d_MSIX_CONFIG %lx
%s(): %i: NQM_MSIX_DBG_TW_SM %lx
%s(): %i: NQM_VF%d_VEC%d_MSIX_INT_ST %lx
%s(): %i: nqm init:
%s(): %i: VF mode: 1PF and %d VFs
nqm_set_vf_mode nvme_set_sq_credits nvme_set_cplq_size nqm_cc_change_interrupt nqm_global_reg_init cn73xx_nqm_irq_handler cn73xx_nqm_delete_admin_sq cn73xx_nqm_disable_sq cn73xx_nqm_create_admin_cq cn73xx_nqm_delete_admin_cq cn73xx_nqm_disable_cq cn73xx_nqm_create_io_cq cn73xx_nqm_delete_io_cq cn73xx_nqm_delete_io_sq cn73xx_nqm_cpl_submit nvme_dump_csrs nqm_init ERROR: %s is suppored on OCTEON3 only
%s: wqe allocation failed
%s: Error !!! Default switch case
%s(): %i: FPA alloc failed
%s(): %i: Error: BDEV info is NULL
%s(): %i: Error: I/O Write Cmd Datatransfer has failed, %lu bytes left
%s(): %i: Can't alloc namespace structure
SATA Device %u init: size %lu
%s: bdev_size %d, sector_size %d
%s(): %i: Error: io_cmd_context missing
%s(): %i: Error: IO error, lba %lu code 0x%x
%s(): %i: Error: io_cmd_context->data_bufs is NULL
Error: dma_data_bufs alloc failed %s(): %i: Error: I/O Read Cmd Datatransfer has failed, %lu bytes left
%s(): %i: Error: PRP List not freed
%s: Invalid opcode
cvmx_pow_work_submit_node sal_complete_oct_linux_bdev_io sal_do_oct_linux_bdev_io sal_bdev_init sal_linux_bdev_process_message sal_register_bdev_handler sal_rdwr_bio_done_resp_handler
(
P
P
Pphandle linux,phandle slice_offset %s(%p, %d, %p): Error: reg %d undefined or out of range
%s(%p, %d, %p): Error: reg_offset 0x%x undefined or out of range
%s: Error: phy info cs4343 datastructure is NULL
sr-stx-cmode-res sr-stx-drv-lower-cm sr-stx-level sr-stx-pre-peak sr-stx-muxsubrate-sel sr-stx-post-peak cx-stx-cmode-res cx-stx-drv-lower-cm cx-stx-level cx-stx-pre-peak cx-stx-muxsubrate-sel cx-stx-post-peak basex-stx-cmode-res basex-stx-drv-lower-cm basex-stx-level basex-stx-pre-peak basex-stx-muxsubrate-sel basex-stx-post-peak %s: No parent node!
#address-cells #size-cells %s: Bad cell count for %s
ranges %s: Could not get reg address
%s: reg: 0x%x
Error: i2c node in device tree missing "reg" field.
Node name: %s
Invalid i2c CSR address 0x%llx in device tree
Out of memory cavium,octeon-7890-twsi cavium,octeon-3860-twsi %s: Error: did not find root i2c bus
%s: Error: could not find match for mux type %s
%s: Something bad happened
%s: Invalid phandle 0x%x
%s: Incompatible parent "%s", must be native OCTEON i2c/twsi bus
Cannot get TWSI node address Error: unknown TWSI node address 0x%llx
simple-bus %s: Error: could not find property %s at node offset %d in the device tree
%s: Error: GPIO entry size %d wrong, must contain phandle, pin and flags
%s: Error: out of memory
%s: Error: pin %d for %s out of range, max: %d
%s: Invalid GPIO phandle for %s
%s: GPIO controller reg field missing for %s
%s: Invalid i2c bus for %s
%s: Error enabling i2c bus for %s
%s(%s): Unknown GPIO type
%s: Interface mode %s for interface 0x%x, ipd_port %d not supported for QSFP
sfp-mac qsfp-mac vitesse,vsc7224 %s: Error %d parsing FDT
%s: Error: reg field missing
%s: Error getting i2c bus
los vitesse,vsc7224-channel %s: Failed finding compatible channel
%s: channel reg is either not present or out of range
direction-tx taps %s: Error: no taps defined for vsc7224 channel %d
%s: Error: channel %d already assigned at %p
%s: Error: tap format error for channel %d
pretap-disable posttap-disable %s: Error: MAC not found for %s channel %d
%s: Error %d with MAC %s phandle for %s
%s: Warning: no (Q)SFP+ slot found for xinterface 0x%x, index %d for channel %d
%s: Error parsing VSC7224 channels
%s: Error: incompatible sfp/qsfp slot, compatible=%s
%s: Missing "eeprom" from device tree for %s
%s: Error: could not determine i2c bus for eeprom for %s
%s: Error parsing eeprom info for %s
%s: Error: out of memory!
%s: Error: unknown compatible string %s for %s
nxp,pca9505 pca9505 nxp,pca9698 pca9698 nxp,pca9534 nxp,pca9535 nxp,pca9536 nxp,pca9537 nxp,pca9538 nxp,pca9539 nxp,pca9554 nxp,pca9554a nxp,pca9555 nxp,pca9555a nxp,pca9557 nxp,pca9574 nxp,pca9575 maxim,max7310 maxim,max7312 maxim,max7313 maxim,max7315 ti,pca6107 ti,tca6408 ti,tca6416 ti,tca6424 pca9534 pca9535 pca9536 pca9537 pca9538 pca9539 pca9554 pca9554a pca9555 pca9555a pca9558 pca9574 pca9575 nxp,pcf8574 nxp,pcf8574a nxp,pc8574 nxp,pca9670 nxp,pca9672 nxp,pca9674 nxp,pca8575 nxp,pcf8575 nxp,pca9671 nxp,pca9673 nxp,pca9675 maxim,max7328 maxim,max7329 ti,tca9554 nxp,pca9540 nxp,pca9542 nxp,pca9543 nxp,pca9544 nxp,pca9545 nxp,pca9546 nxp,pca9547 cvmx_fdt_translate_address
b
b j ( j( ( j0 ( j@ ( jH jX jh jx j j j j j j j j k k k( k8 kH kX kh kx k k k k k k k k k k k k l l l l l0 l@ lP l` lp l l l l l l l cvmx_fdt_get_i2c_bus l m m m m0 m@ mP
mX cvmx_octeon_i2c_reg_to_bus cvmx_fdt_get_twsi_gpio_bus_addr cvmx_fdt_gpio_get_info_phandle cvmx_fdt_gpio_set __cvmx_gpio_cfg cvmx_fdt_gpio_get cvmx_sfp_set_ipd_port __cvmx_fdt_parse_vsc7224 cvmx_fdt_parse_vsc7224_channels cvmx_helper_fdt_parse_sfp_info cvmx_parse_sfp_eeprom cvmx_fdt_parse_cs4343 cvmx_fdt_parse_cs4343_slice , function: assertion "%s" failed: file "%s", line %d%s%s
((((( AAAAAABBBBBB ((((( AAAAAABBBBBB C WARNING: boot descriptor version mismatch between bootloader and Octeon executive.
WARNING: unpredictable behavior may result.
WARNING: CVMX boot descriptor version mismatch.
Warning: Bootmem descriptor version is newer than expected
mem list is empty!
cvmx_phys_to_ptr() passed a zero address
List of currently allocated named bootmem blocks:
No named bootmem blocks exist.
ERROR: no memory for cvmx_bootmem descriptor provided
ERROR: requested memory size too large, truncating to maximum size
FATAL ERROR: unable to allocate memory for bootmem descriptor!
__octeon_bootmem_phy_alloc __octeon_bootmem_reserve_memory #%d %p
P` P0 PH P` P0 P0cvmx_ptr_to_phys() passed a NULL pointer
Failed allocating debug globals, spinining.
WP WH W@ W8 W0 W( V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V W W _0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Yh X X X X X X X X X X X X X X X X X X X _h X Y X X X X [ ` X _ Zx X X \0 X X X X X X X X X X X X [` X X X X X X Y X [X X ` Z _ X Z\ Z X X ]H X X X X X _( X X X X X X ^ :x :@0123456789ABCDEF memfile: out of memory
Dumping files on core %d
begin 644 `
end
Done dumping files on core %d
WARNING:
0123456789abcdef (null) INF inf NAN nan \ | T 8 h @ H h h h 4 t h @ L h h h D L ( @ \ ( 8 ( 0000000000000000 0 ̀ ̀ D ̀ ̀ ̀ ̀ ̀ ϔ T ̀ p ̀ d ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ D ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ Ҽ ̀ Ґ ̀ ̀ P ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ ̀ < ψ ̀ ̀ М ̀ Ҽ ψ ̀ ̀ ̀ ψ 0000000000000000 ( ( ( ( ( ( ( d ( H ( X ( ( ( ( ( ( ( ( ( ( ( ( l ( ( l ( ( ( x ( l ( ( ( ( ( ( ( ( ( ( ( 0 ` ( ( H p t ( x ` p ( ( ( ` 0000000000000000Infinity NaN POSIX <Ҳ؉9I#ը32D=%[ό
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