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FrF,XX`m@[vT (Ix َ!em`OᦀPJq@ h m @ FIRMWARE_CS35L56 4 FW_HL_STT FIRMWARE_CS35L56_HALO_STATE <
FW_HL_HARTBAT FIRMWARE_CS35L56_HALO_HEARTBEAT 4 FW_PWR_MD FIRMWARE_CS35L56_POWER_MODE <
FW_ADO_BLK_SZ FIRMWARE_CS35L56_AUDIO_BLK_SIZE 8 FW_RFCLK_SRC FIRMWARE_CS35L56_REFCLK_SRC
D FW_PLL_RFCLK_FRQ FIRMWARE_CS35L56_PLL_REFCLK_FREQ D FW_PLL_MCLK_FRQ%FIRMWARE_CS35L56_REFCLK_PLL_FREQ_MCLK 0 FW_I2S_EN FIRMWARE_CS35L56_I2S_EN 8 FW_BOT_RASN FIRMWARE_CS35L56_BOOT_REASON @
FW_REFCLK_DET "FIRMWARE_CS35L56_REFCLK_DETECT_32K < FW_HW_CLCK_STT FIRMWARE_CS35L56_HW_CLOCK_STATE @ FW_CP_MTR_ENBL !FIRMWARE_CS35L56_CPU_METER_ENABLE D FW_MPS_OVRRN_FLG "FIRMWARE_CS35L56_MIPS_OVERRUN_FLAG D FW_MIPS_OR_HBN $FIRMWARE_CS35L56_MIPS_OVERRUN_HB_NUM AUDIO_SYSTEM 4
AS_ADO_STT AUDIO_SYSTEM_AUDIO_STATE 0
AS_LST_CMD AUDIO_SYSTEM_LAST_CMD H STRM_TO_SYNTH_DN &AUDIO_SYSTEM_STRM_ACTIVE_TO_SYNTH_DONE
H
SYNTH_TO_STRM *AUDIO_SYSTEM_SYNTH_ACTIVE_TO_STREAM_ACTIVE @
PLL_RS_REQ &AUDIO_SYSTEM_AMP_PLL_UNLOCK_RESYNC_REQ H
STRM_TO_SYNTH *AUDIO_SYSTEM_STREAM_ACTIVE_TO_SYNTH_ACTIVE ( AS_ERRRAUDIO_SYSTEM_ERROR 8
AS_PAK_CP_LAD AUDIO_SYSTEM_PEAK_CPU_LOAD < AS_CRRNT_CP_LAD AUDIO_SYSTEM_CURRENT_CPU_LOAD @ AS_SYNTHSS_ENBLD AUDIO_SYSTEM_SYNTHESIS_ENABLED $ 4 AS_ADO_STTSAUDIO_SYSTEM_AUDIO_STATUS % 0 AS_PRJCT_IDAUDIO_SYSTEM_PROJECT_ID & 0 AS_CHNNL_IDAUDIO_SYSTEM_CHANNEL_ID ' 8 AS_SNPSHT_ID AUDIO_SYSTEM_SNAPSHOT_ID \ ACTISONIC < ACTISONIC_ENABLE ACTISONIC_ACTISONIC_ENABLE CLIP_DETECT INPUT_CONDITIONER T IC_EN ?INPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_ENABLE \ IC_CH_BAL AINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL d IC_CH_BALSMHINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL_SMOOTH h IC_MM_XO_ENMINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_MONOMIX_XOVER_ENABLE d
IC_H_XO_EN JINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_HALF_XOVER_ENABLE / h IC_PPU_H_XO_BALKINPUT_CONDITIONER_INPUT_CONDITIONER_PPU_CTRL_STRUCT_INP_COND_HALF_XOVER_BAL 0
INPUT_ENHANCE \ IE_DRC_LD_OP_LVL 8INPUT_ENHANCE_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL & H
IE_DRC_OP_LVL +INPUT_ENHANCE_DRC_1_STRUCT_DRC_OUTPUT_LEVEL + X IE_ENABLE < XU22_MR_BYPASS SDCA_XU22_MAIN_RENDER_BYPASS C 4 XU22_FDL_STATUSSDCA_XU22_FDL_STATUS D 8 XU22_FDL_SET_IND SDCA_XU22_FDL_SET_INDEX E < XU22_FDL_HOS_REQ SDCA_XU22_FDL_HOST_REQUEST F @ XU24_SPK_SNS_BYP SDCA_XU24_SPEAKER_SENSE_BYPASS H @ CS21_MR_SFI'SDCA_CS21_MAIN_RENDER_SAMPLE_FREQ_INDEX J @ CS24_SNS_SFI !SDCA_CS24_SENSE_SAMPLE_FREQ_INDEX L D CS25_REF_SFI %SDCA_CS25_REFERENCE_SAMPLE_FREQ_INDEX N H CS26_ULTRASO_SFI &SDCA_CS26_ULTRASONIC_SAMPLE_FREQ_INDEX O @ PDE22_MR_REQ_PS#SDCA_PDE22_MAIN_RENDER_REQUESTED_PS P @ PDE22_MR_ACT_PS SDCA_PDE22_MAIN_RENDER_ACTUAL_PS Q @ PDE24_SNS_REQ_PS SDCA_PDE24_SENSE_REQUESTED_PS R < PDE24_SNS_ACT_PS SDCA_PDE24_SENSE_ACTUAL_PS S D PDE23_TRD_REQ_PS "SDCA_PDE23_TRANSDUCER_REQUESTED_PS T @ PDE23_TRD_ACT_PS SDCA_PDE23_TRANSDUCER_ACTUAL_PS W 8 TG23_TONE_DIVIDE SDCA_TG23_TONE_DIVIDER @ XU22_FDL_MES_OFF SDCA_XU22_FDL_MESSAGE_OFFSET @ XU22_FDL_MES_LEN SDCA_XU22_FDL_MESSAGE_LENGTH @ ! PPU (
PPU_ENABLE PPU_PPU_ENABLE # EVENT_LOGGER < EVLOG_HEADER EVENT_LOGGER_EVENT_LOG_HEADER 0 EVLOG_EN EVENT_LOGGER_ENABLED 8
BUFFER_STATUS EVENT_LOGGER_BUFFER_STATUS @ EVLOG_ST_OFF EVENT_LOGGER_START_STREAM_OFFSET 8 WAS_DISABLED EVENT_LOGGER_WAS_DISABLED
< EVLOG_TS_SHIFT EVENT_LOGGER_TIMESTAMP_SHIFT X * ASP_MIXER 8 ASP_MIX_ENABLE ASP_MIXER_ASP_MIX_ENABLE + AUDIO_WAVETABLE , BOOSTEMP H bt_en 2BOOSTEMP_BOOSTEMP_CTRL_STRUCT_FIRMWARE_BOOSTEMP_EN 4 8 bt_rspk"BOOSTEMP_BOOSTEMP_CTRL_STRUCT_RSPK 5 H bt_temp_est,BOOSTEMP_BOOSTEMP_CTRL_STRUCT_BOOST_TEMP_EST
EVENT_HANDLER GPIO - AUTO_CALIBRATION
AC_SGS_THRESH sAUTO_CALIBRATION_PICL_RESISTANCE_CALIBRATION_RX_CMPST_0_Z_MEASURE_PILOT_TONE_CMPST_0_SINEGENERATORSENSE_0_THRESHOLD T AC_R1 8 SWDE_DE_S_F3_B0SWDE_D_ENH_SIDE_FILT_3_B0 ? 8 SWDE_DE_S_F3_B1SWDE_D_ENH_SIDE_FILT_3_B1 @ 8 SWDE_DE_S_F3_B2SWDE_D_ENH_SIDE_FILT_3_B2 A < SWDE_DE_S_v3_MA1 SWDE_D_ENH_SIDE_FILT_3_MA1 B < SWDE_DE_S_F3_MA2 SWDE_D_ENH_SIDE_FILT_3_MA2 C 4 SWDE_DE_M_SCALESWDE_D_ENH_MID_SCALE D 4 SWDE_DE_M_SHIFTSWDE_D_ENH_MID_SHIFT E 4 SWDE_DE_S_SCALESWDE_D_ENH_SIDE_SCALE F 4 SWDE_DE_S_SHIFTSWDE_D_ENH_SIDE_SHIFT I 0 SWDE_XFADE_BAL SWDE_SWDE_BALANCE 4 BOOT_BEEP < BOOT_BEEP_ENABLE BOOT_BEEP_BOOT_BEEP_ENABLE 4
DSP_BEEP_FREQ BOOT_BEEP_DSP_BEEP_FREQ 8 DSP_BEEP_LEVEL BOOT_BEEP_DSP_BEEP_LEVEL 8 bb_dsp_beep_durBOOT_BEEP_DSP_BEEP_DURATION 4
GPI_BEEP_FREQ BOOT_BEEP_GPI_BEEP_FREQ 8 GPI_BEEP_LEVEL BOOT_BEEP_GPI_BEEP_LEVEL 8 bb_gpi_beep_durBOOT_BEEP_GPI_BEEP_DURATION 4 BEEP_PENDING BOOT_BEEP_BEEP_PENDING $ / SHARED_PATCHING_STRUCTURE P SPTCH_MD_SLW_FRM -SHARED_PATCHING_STRUCTURE_MBDRC_SLEW_N_FRAMES P L
SPE_CONFIG 2SHARED_PATCHING_STRUCTURE_STREAM_PREEMPTION_CONFIG \ RDL3_EN_DMGA